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AD1953

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Table XVI. Data Capture Register Write Format

Byte 0

Byte 1

Byte 2

Byte 3

00000, R/Wb, Adr[9:8]

Adr[7:0]

00000, ProgCount[8:6]

ProgCount[5:0], RegSel[1:0]

1, 2

NOTES

1. ProgCount[8:0] = value of program counter where trap occurs (see Table XXI).

2. RegSel[1:0] selects one of four registers (see Data Capture Register section).

Table XVII. Data_Capture_Serial Out Register (Address and Register Select) Write Format

Byte 0

Byte 1

Byte 2

Byte 3

00000, R/Wb, Adr[9:8]

Adr[7:0]

00000, ProgCount[8:6]

ProgCount[5:0], RegSel[1:0]

1, 2

NOTES

1. ProgCount[8:0] = value of program counter where trap occurs (see Table XXI).

2. RegSel[1:0] selects one of four registers (see Data Capture Registers section).

Table XVIII. Data Capture Read Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

00000, R/Wb, Adr[9:8]

Adr[7:0]

00000000

Data[23:16]

Data[15:8]

Data[7:0]

Table XIX. Safeload Register Write Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

00000, R/Wb, Adr[9:8]

Adr[7:0]

ParamAdr[7:0]

00, Param[21:16]

Param[15:8]

Param[7:0]

INITIALIZATION

Power-Up Sequence

The AD1953 has a built-in power-up sequence that initializes

the contents of all internal RAMs. During this time, the contents

of the internal program boot ROM are copied to the internal

program RAM, and likewise the SPI parameter RAM is filled

with values from its associated boot ROM. The data memories

are also cleared during this time.

The boot sequence lasts for 1024 MCLK cycles and starts on

the rising edge of the RESETB pin. Since the boot sequence

requires a stable master clock, the user should avoid writing to

or reading from the SPI registers during this period of time.

Note that the default power-on state of the internal clock mode

circuitry is 512

× f

S, or about 24 MHz for normal audio sample

rates. This mode bypasses all the internal clock doublers and

allows the external master clock to directly operate the DSP

core. If the external master clock is 256

× f

S, the boot sequence will

operate at this reduced clock rate and take slightly longer to

complete. After the boot sequence has finished, the clock modes

may be set via the SPI port. For example, if the external master

clock frequency is 256

× fS clock, the boot sequence would

take 1024 256

× f

S clock cycles to complete, after which an

SPI write could occur to put the AD1953 in 256

× f

S mode.

The default state of the MCLK input selector is MCLK0. Since

this input selector is controlled using the SPI port, and the SPI

port cannot be written to until the boot sequence is complete,

there must be a stable master clock signal present on the MCLK0

pin at startup.

Setting the Clock Mode

The AD1953 contains a clock doubler circuit that is used to

generate an internal 512

× f

S clock when the external clock is

256

× f

S. The clock mode is set by writing to Bit <2> of Control

When the clock mode is changed, it is possible that a glitch will

occur on the internal MCLK signal. This may cause the proces-

sor to inadvertently write an incorrect value into the data RAM,

which could cause an audio pop or click sound. To prevent this,

it is recommended that the following procedure be followed:

1. Assert the soft power-down bit (Bit <6> in Control Register 1)

to stop the internal MCLK.

2. Write the desired clock mode into Bit <2> of Control Register 2.

3. Wait at least 1 ms while the clock doublers settle.

4. Deassert the soft power-down bit.

An alternative procedure is to initiate a soft shutdown of the

processor core by writing a 1 to the halt program bit in Control

by a shutdown of the DSP core. Once the core is shut down

(which can be verified by reading Bit <1> from Control Register 1,

or by waiting at least 20 ms), the new clock mode can be

programmed by writing to Bit <2> of Control Register 2. The

DSP core can then be restarted by clearing the halt program bit

in Control Register 1.

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