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AD1953

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SERIAL DATA INPUT/OUTPUT PORTS

The AD1953’s flexible serial data input port accepts data in twos

complement, MSB first format. The left channel data field always

precedes the right channel data field. The serial mode is set by

using mode select bits in the SPI control register. In all modes

except for the right-justified mode, the serial port will accept an

arbitrary number of bits up to a limit of 24 (extra bits will not

cause an error, but they will be truncated internally). In the right-

justified mode, SPI control register bits are used to set the word

length to 16, 20, or 24 bits. The default on power-up is 24-bit mode.

Proper operation of the right-justified mode requires that there

be exactly 64 BCLK per audio frame.

Serial Data Input/Output Modes

Figure 19 shows the serial input modes. For the left-justified

mode, LRCLK is HIGH for the left channel, and LOW for the

right channel. Data is sampled on the rising edge of BCLK. The

MSB is left-justified to an LRCLK transition, with no MSB delay.

The left-justified mode can accept any word length up to 24 bits.

In I

2S mode, LRCLK is low for the left channel and high for the

right channel. Data is valid on the rising edge of BCLK. The MSB

is left-justified to an LRCLK transition but with a single BCLK

period delay. The I

2S mode can be used to accept any number

of bits up to 24.

In right-justified mode, LRCLK is high for the left channel and

low for the right channel. Data is sampled on the rising edge

of BCLK. The start of data is delayed from the LRCLK edge

by 16, 12, or 8 BCLK intervals, depending on the selected

word length. The default word length is 24 bits; other word

lengths are set by writing to Bits <1:0> of Control Register 1.

In right-justified mode, it is assumed that there are 64 BCLKs

per frame.

RIGHT CHANNEL

LEFT CHANNEL

LRCLK

BCLK

SDATA

LSB

LEFT CHANNEL

RIGHT CHANNEL

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

DSP MODE – 16 BITS TO 24 BITS PER CHANNEL

NOTES

1. DSP MODE DOESN’T IDENTIFY CHANNEL

2. LRCLK NORMALLY OPERATES AT

fS EXCEPT DSP MODE, WHICH IS 2

3. BCLK FREQUENCY IS NORMALLY 64

LRCLK BUT MAY BE OPERATED IN BURST MODE

I2S MODE – 16 BITS TO 24 BITS PER CHANNEL

RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL

LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL

MSB

Figure 19. Serial Input Modes

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