AD1953_15 datasheet(19/36 Pages) AD

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REV. 0

AD1953

–19–

The detailed data format diagram for continuous-mode opera-

tion is given in SPI Read/Write data formats.

A sample timing diagram for a single SPI WRITE operation to

the parameter RAM is shown in Figure 16.

Table I. SPI Word Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

00000, R/Wb, adr[9:8]

Adr[7:0]

Data

A sample timing diagram of a single SPI READ operation is

shown in Figure 17. The COUT pin goes from three-state to

driven at the beginning of Byte 2. Bytes 0 and 1 contain the

address and R/W bit, and Bytes 2 to 4 carry the data. The exact

format is shown in Tables VIII to XIX.

The AD1953 has several mechanisms for updating signal-

processing parameters in real time without causing loud pops or

clicks. In cases where large blocks of data need to be downloaded,

the DSP core can be shut down and new data loaded, and the

core can then be restarted. The shutdown and restart mecha-

nisms employ a gradual volume ramp to prevent clicks and pops.

In cases where only a few parameters need to be changed (for

example, a single biquad filter), a safeload mechanism is used

that allows a block of SPI registers to be transferred to the

parameter RAM within a single audio frame while the core is

running. The safeload mode uses internal logic to prevent con-

tention between the DSP core and the SPI port.

SPI Address Decoding

Table II shows the address decoding used in the SPI port. The

SPI address space encompasses a set of registers and two RAMs,

one for holding signal-processing parameters and one for holding

the program instructions. Both of the RAMs are loaded on

power-up from on-board boot ROMs.

BYTE 0

BYTE 1

BYTE 4

CDATA

CCLK

CLATCH

Figure 16. Sample of SPI WRITE Format (Single-Write Mode)

BYTE 0

CDATA

CCLK

CLATCH

COUT

BYTE 1

HI-Z

DATA

XXX

DATA

HI-Z

Figure 17. Sample of SPI READ Format (Single-Read Mode)

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