ADE7166_15 datasheet(49/152 Pages) AD

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 49 of

152

Table 45. Interrupt Enable 3 SFR (MIRQENH, Address 0xDB)

Bit

Interrupt Enable Bit

Description

[7:6]

Reserved

Reserved.

WFSM

When this bit is set to Logic 1, the WFSM flag set creates a pending ADE interrupt to the 8052 core.

PKI

When this bit is set to Logic 1, the PKI flag set creates a pending ADE interrupt to the 8052 core.

PKV

When this bit is set to Logic 1, the PKV flag set creates a pending ADE interrupt to the 8052 core.

CYCEND

When this bit is set to Logic 1, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.

ZXTO

When this bit is set to Logic 1, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.

When this bit is set to Logic 1, the ZX flag set creates a pending ADE interrupt to the 8052 core.

ANALOG INPUTS

Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

ADE7569 has two fully differential voltage input channels. The

maximum differential input voltage for the VP/VN and IP/IN

input pairs is ±0.4 V.

For the ADE7116/ADE7156/ADE7166/ADE7169, PGA1 = 1 is not

recommended because, at full scale, when both IPA and IPB are

180° out of phase, the ADC can be overranged. It is recom-

mended, for these products, that PGA1 = 2, 4, 8, or 16 be used.

Each analog input channel has a programmable gain amplifier

(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The

gain selections are made by writing to the GAIN register (see

Table 38 and Figure 41). Bit 2 to Bit 0 select the gain for the PGA

in the current channel, and Bit 7 to Bit 5 select the gain for the

PGA in the voltage channel. Figure 42 shows how a gain selec-

tion for the current channel is made using the gain register.

000

654

GAIN REGISTER*

CURRENT AND VOLTAGE CHANNELS PGA CONTROL

PGA2 GAIN SELECT

000 = × 1

001 = × 2

010 = × 4

011 = × 8

100 = × 16

PGA1 GAIN SELECT

000 = × 1

001 = × 2

010 = × 4

011 = × 8

100 = × 16

RESERVED

*REGISTER CONTENTS SHOW POWER-ON DEFAULTS.

ADDR:

0x1B

CFSIGN_OPT

Figure 41. Analog Gain Register

K × VIN

000

543

210

GAIN[7:0]

GAIN (K)

SELECTION

VIN

Figure 42. PGA in Current Channel

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