ADE7166_15 datasheet(73/152 Pages) AD

73 / 152 page

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 73 of

152

APPARENT ENERGY CALCULATION

The apparent energy is given as the integral of the apparent power.

∫

Power

Apparent

Energy

Apparent

)

(

(33)

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

ADE7569 achieve the integration of the apparent power signal

by continuously accumulating the apparent power signal in an

internal 48-bit register. The apparent energy register

(VAHR[23:0], Address 0x07) represents the upper 24 bits of this

internal register. This discrete time accumulation or summation

is equivalent to integration in continuous time. Equation 34

expresses the relationship.

⎭

⎬

⎫

⎩

⎨

⎧

∑

∞

→

)

(

lim

Power

Apparent

Energy

Apparent

(34)

where:

n is the discrete time sample number.

T is the sample period.

The discrete time sample period (T) for the accumulation

ADE7566/ADE7569 is 1.22 μs (5/MCLK).

Figure 77 shows this discrete time integration or accumulation.

The apparent power signal is continuously added to the internal

energy theoretically remains positive.

The 49 bits of the internal register are divided by VADIV. If the

value in the VADIV register (Address 0x26) is 0, the internal

apparent energy register is divided by 1. VADIV is an 8-bit,

unsigned register. The upper 24 bits are then written in the

24-bit apparent energy register (VAHR[23:0], Address 0x07).

The RVAHR register (Address 0x08), which is 24 bits long, is

provided to read the apparent energy. This register is reset to 0

after a read operation.

Note that the apparent energy register is unsigned. By setting the

VAEHF bit (Bit 2) and the VAEOF bit (Bit 5) in the Interrupt

Enable 2 SFR (MIRQENM, Address 0xDA), the device can be

configured to issue an ADE interrupt to the 8052 core when the

apparent energy register is half-full or when an overflow occurs.

The half-full interrupt for the unsigned apparent energy register

is based on 24 bits as opposed to 23 bits for the signed active

energy register.

Integration Time Under Steady Load: Apparent Energy

As mentioned in the Apparent Energy Calculation section, the

discrete time sample period (T) for the accumulation register is

1.22 μs (5/MCLK). With full-scale sinusoidal signals on the

analog inputs and the VAGAIN register (Address 0x1F) set to

0x000, the average word value from the apparent power stage is

0x1A36E2 (see the Apparent Power Calculation section). The

maximum value that can be stored in the apparent energy

word value is added to the internal register, which can store 248

or 0xFFFF,FFFF,FFFF before it overflows. Therefore, the

integration time under these conditions with VADIV = 0 is

calculated as follows:

Time =

min

sec

199

0xD055

FFFF

FFFF,

0xFFFF,

(35)

When VADIV is set to a value different from 0, the integration

time varies, as shown in Equation 36.

Time

= TimeWDIV = 0 × VADIV

(36)

VADIV

APPARENT POWER

Irms

VAHR[23:0]

APPARENT POWER OR Irms IS

ACCUMULATED (INTEGRATED)

IN THE APPARENT ENERGY

TIME (nT)

APPARENT

POWER SIGNAL = P

Figure 77. Apparent Energy Calculation

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