ADE7166_15 datasheet(20/152 Pages) AD

20 / 152 page

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 20 of

152

Pin No.

Mnemonic

Description

LCDVA

In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or

an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an

analog input. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this

pin is an analog input, a resistor should be connected between this pin and LCDVP1 to generate an inter-

mediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this

pin and LCDVB to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVA and LCDVB are

internally connected (see the LCD Driver section).

LCDVP1

In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or

an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an

analog input. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and

LCDVP2. When this pin is an analog input, a resistor should be connected between this pin and LCDVA to

generate an intermediate voltage for the LCD driver. Another resistor must be connected between LCDVP1

and DGND to generate another intermediate voltage (see the LCD Driver section).

20 to 35

FP15 to FP0

LCD Segment Output 0 to LCD Segment Output 15.

P1.1/TxD

General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).

P1.0/RxD

General-Purpose Digital I/O Port 1.0/Receiver Data Input (Asynchronous).

P0.7/SS/T1

General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input.

P0.6/SCLK/T0

General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input.

P0.5/MISO

General-Purpose Digital I/O Port 0.5/Data Input for SPI Port.

P0.4/MOSI/SDATA

General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line.

P0.3/CF2

General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives

instantaneous active, reactive, Irms, or apparent power information.

P0.2/CF1/RTCCAL

General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic

Output. The CF1 logic output gives instantaneous active, reactive, Irms, or apparent power information. The

RTCCAL logic output gives access to the calibrated RTC output.

SDEN/P2.3

Serial Download Mode Enable/General-Purpose Digital I/O Port 2.3. This pin is used to enable serial

download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily

becomes an input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin

momentarily goes high and then user code is executed. If the pin is pulled down on reset, the embedded

serial download/debug kernel executes, and this pin remains low during the internal program execution.

After reset, this pin can be used as a digital output port pin (P2.3).

BCTRL/INT1/P0.0

Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic

input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left

open, the connection between VDD or VBAT and VSWOUT is selected internally.

XTAL2

A crystal can be connected across this pin and XTAL1 to provide a clock source for the ADE7116/ADE7156/

ADE7166/ADE7169. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or

by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin.

XTAL1

An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected

across XTAL1 and XTAL2 to provide a clock source for the ADE7116/ADE7156/ADE7166/ADE7169. The clock

frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.

INT0

External Interrupt Input 0.

49, 50

VP, VN

Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum

differential level of ±400 mV for specified operation. This channel also has an internal PGA.

This pin is used as an input for emulation. When held high, this input enables the device to fetch code from

internal program memory locations. The ADE7116/ADE7156/ADE7166/ADE7169 do not support external

code memory. This pin should not be left floating.

52, 53

IPA, IN

Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum

differential level of ±400 mV for specified operation. This channel also has an internal PGA.

AGND

This pin provides the ground reference for the analog circuitry.

IPB

Analog Input for Second Current Channel (IPB). This input is fully differential with a maximum differential

level of ±400 mV, referred to IN for specified operation. This channel also has an internal PGA.

RESET

Reset Input, Active Low.

REFIN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

1.2 V ± 0.1% and a maximum temperature coefficient of 50 ppm/°C. This pin should be decoupled with a 1

μF capacitor in parallel with a ceramic 100 nF capacitor.

VBAT

Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when

the battery is selected as the power supply for the ADE7116/ADE7156/ADE7166/ADE7169.

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