ADE7166_15 datasheet(95/152 Pages) AD

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 95 of

152

INTERRUPT FLAGS

The interrupt flags and status flags associated with the interrupt vectors are shown in Table 82 and Table 83. Most of the interrupts have

flags associated with them.

Table 82. Interrupt Flags

Interrupt Source

Flag

Bit Name

Description

IE0

TCON.1

IE0

External interrupt 0.

TF0

TCON.5

TF0

Timer 0.

IE1

TCON.3

IE1

External interrupt 1.

TF1

TCON.7

TF1

Timer 1.

RI + TI

SCON.1

Transmit interrupt.

SCON.0

Receive interrupt.

TF2 + EXF2

T2CON.7

TF2

Timer 2 overflow flag.

T2CON.6

EXF2

Timer 2 external flag.

ITEMP (Temperature ADC)1

N/A

Temperature ADC interrupt. Does not have an interrupt flag associated with it.

IPSM (Power Supply)

IPSMF.6

FPSM

PSM interrupt flag.

IADE (Energy Measurement DSP)

MIRQSTL.7

ADEIRQFLAG

Read MIRQSTH, MIRQSTM, MIRQSTL.

1 This feature is not available in the ADE7116.

Table 83. Status Flags

Interrupt Source

Flag

Bit Address

Description

ITEMP (Temperature ADC)1

N/A

Temperature ADC interrupt. Does not have a status flag associated with it.

ISPI/I2CI

SPI2CSTAT

N/A

SPI interrupt status register.

SPI2CSTAT

N/A

I2C interrupt status register.

IRTC (RTC Interval Timer)

TIMECON.7

MIDNIGHT

RTC midnight flag.

TIMECON.2

ALARM

RTC alarm flag.

WDT (Watchdog Timer)

WDCON.2

WDS

Watchdog timeout flag.

1 This feature is not available in the ADE7116.

A functional block diagram of the interrupt system is shown in

Figure 89. Note that the PSM interrupt is the only interrupt in

the highest priority level.

If an external wake-up event occurs to wake the ADE7116/

ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 from PSM2

mode, a pending external interrupt is generated. When the EX0

bit (Bit 0) or the EX1 bit (Bit 2) in the interrupt enable SFR (IE,

Address 0xA8) is set to enable external interrupts, the program

counter is loaded with the IE0 or IE1 interrupt vector. The IE0

and IE1 interrupt flags (Bit 1 and Bit 3, respectively) in the

Timer/Counter 0 and Timer/Counter 1 control SFR (TCON,

Address 0x88) are not affected by events that occur when the

8052 MCU core is shut down during PSM2. See the Power

Supply Management (PSM) Interrupt section.

The RTC, temperature ADC, and I2C/SPI interrupts are latched

such that pending interrupts cannot be cleared without entering

their respective interrupt service routines. Clearing the RTC

midnight flags and alarm flags does not clear a pending RTC

interrupt. Similarly, clearing the I2C/SPI status bits in the SPI

Interrupt Status SFR (SPISTAT, Address 0xEA) does not cancel

a pending I2C/SPI interrupt. These interrupts remain pending

until the RTC or I2C/SPI interrupt vectors are enabled. Their

respective interrupt service routines are entered shortly

thereafter.

Figure 89 shows how the interrupts are cleared when the

interrupt service routines are entered. Some interrupts with

multiple interrupt sources are not automatically cleared;

specifically, the PSM, ADE, UART, and Timer 2 interrupt

vectors. Note that the INT0 and INT1 interrupts are only

cleared only if the external interrupt is configured to be

triggered by a falling edge by setting IT0 (Bit 0) in the

Timer/Counter 0 and Timer/Counter 1 control SFR (TCON,

Address 0x88). If INT0 or INT1 is configured to interrupt on a

low level, the interrupt service routine is reentered until the

respective pin goes high.

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