ADE7166_15 datasheet(71/152 Pages) AD

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 71 of

152

Line Cycle Reactive Energy Accumulation Mode

Var Absolute Accumulation Mode

In line cycle reactive energy accumulation mode, the energy

accumulation of the ADE7169/ADE7569 can be synchronized

to the voltage channel zero crossing so that reactive energy can

be accumulated over an integral number of half-line cycles. The

advantages of this mode are similar to the ones described in the

Line Cycle Active Energy Accumulation Mode section.

The ADE7169/ADE7569 are placed in absolute accumulation

mode by setting the ABSVARM bit (Bit 3) in the ACCMODE

reactive energy accumulation is done by using the absolute

reactive power and ignoring any occurrence of power below the

no load threshold for the reactive energy (see Figure 74). The CF

pulse also reflects this accumulation method when in the

absolute accumulation mode. The default setting for this mode is

off. Transitions in the direction of power flow and no load

threshold are active in this mode.

In line cycle active energy accumulation mode, the

ADE7169/ADE7569 accumulate the reactive power signal in

the LVARHR register (Address 0x06) for an integral number of

line cycles, as shown in Figure 75. The number of half-line cycles

is specified in the LINCYC register (Address 0x12). The

ADE7169/ADE7569 can accumulate active power for up to

65,535 half-line cycles.

REACTIVE ENERGY

NO-LOAD

THRESHOLD

NO-LOAD

THRESHOLD

REACTIVE POWER

Because the reactive power is integrated on an integral number

of line cycles, the CYCEND flag (Bit 2) in the Interrupt Status 3

SFR (MIRQSTH, Address 0xDE) is set at the end of an active

energy accumulation line cycle. If the CYCEND enable bit

(Bit 2) in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB)

is set, the 8052 core has a pending ADE interrupt. The ADE

interrupt stays active until the CYCEND status bit is cleared

(see the Energy Measurement Interrupts section). Another

calibration cycle starts as soon as the CYCEND flag is set. If

the LVARHR register (Address 0x06) is not read before a new

CYCEND flag is set, the LVARHR register is overwritten by a

new value.

Figure 74. Reactive Energy Accumulation in Absolute Accumulation Mode

Reactive Energy Pulse Output

The ADE7169/ADE7569 provide all the circuitry with a pulse

output whose frequency is proportional to reactive power (see

the Energy-to-Frequency Conversion section). This pulse

frequency output uses the calibrated signal after VARGAIN,

and its behavior is consistent with the setting of the reactive

energy accumulation mode in the ACCMODE register

(Address 0x0F). The pulse output is active low and should

preferably be connected to an LED, as shown in Figure 80.

When a new half-line cycle is written in the LINCYC register

(Address 0x12), the LVARHR register is reset, and a new

accumulation starts at the next zero crossing. The number of

half-line cycles is then counted internally until the value

programmed in LINCYC is reached. This implementation

provides a valid measurement at the first CYCEND interrupt

after writing to the LINCYC register. The line reactive energy

accumulation uses the same signal path as the reactive energy

accumulation. The LSB size of these two registers is equivalent.

LPF1

OUTPUT

FROM

LPF2

FROM VOLTAGE

CHANNEL ADC

LINCYC[15:0]

ZERO-CROSSING

DETECTION

LVARHR[23:0]

CALIBRATION

CONTROL

VARDIV[7:0]

VAROS[15:0]

VARGAIN[11:0]

DIGITAL-TO-FREQUENCY

CONVERTER

ACTIVE ENERGY

IS ACCUMULATED IN

THE INTERNAL REGISTER,

AND THE LWATTHR

AT THE END OF THE LINCYC

HALF-LINE CYCLES

Figure 75. Line Cycle Reactive Energy Accumulation Mode

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