AN2021 datasheet(9/39 Pages) STMICROELECTRONICS

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AN2021

Modified features

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Software impact

In case the optional 32 kHz is not used, the OFF32 bit of the RTCCON register must be set.

Prior to setting the OFF32 bit in the RTCCON register, the RTC must be enabled by setting

RTCEN, bit 4 of XPERCON, and XPEN, bit 2 of SYSCON.

1.2

XRAM

The ST10F272B and ST10F272E devices do not have the same size of XRAM. Each

configuration is detailed hereafter.

1.2.1

ST10F272B’s XRAM

The ST10F269 and the ST10F272B have the same size of extension XRAM: 10 Kbytes.

The XRAM of the ST10F269 is divided into two ranges being XRAM1 of 2 Kbytes and

XRAM2 of 8 Kbytes:

●

The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN and XRAM1EN,

bit 2 of SYSCON register and of XPERCON register, respectively, must both be set).

●

The XRAM2 address range is 00’C000h - 00’DFFFh if enabled (XPEN and XRAM2EN,

bit 2 of SYSCON register and bit 3 of XPERCON register, respectively, must both be

set).

The XRAM of the ST10F272 is divided into two ranges, XRAM1 of 2 Kbytes (compatible with

the ST10F269) and XRAM2 of 8 Kbytes with a user re-programmable address range and

the StandBy mode.

●

The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN and XRAM1EN,

bit 2 of SYSCON register and bit 2 of XPERCON register must both be set).

●

The XRAM2 address range is 09’0000h - 09’1FFFh, by default (mirrored every

16 Kbytes in the range 09’0000h -0F’FFFFh), if enabled (XPEN and XRAM2EN, bit 2 of

SYSCON register and bit 3 of XPERCON register, must both be set).

Hardware impact

None.

Software impact

There is no change in the enabling of the XRAM blocks: XPERCON register bits, XRAM1EN

and XRAM2EN, and SYSCON register bit, XPEN, are used to enable them.

The memory mapping of the application is impacted by the difference in XRAM2 location. A

new register has been created in order to allow the user to remap XRAM2 (please refer to

Section 4.1: XADRS3 register on page 28 for details).

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