AN2021 datasheet(29/39 Pages) STMICROELECTRONICS

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AN2021

New registers

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4.1.2

Software impact for the ST10F272B

On ST10F272B, this register must be programmed by the user before accessing XRAM2 so

that:

●

RGSZ defines an 8 Kbyte window size. RGSZ = 0101b

●

RGSAD defines bits 8 to 19 of the window start address aligned to an 8 Kbyte

boundary (the least significant bits of the field are not relevant).

By programming XADRS3 to 0C05h, the XRAM2 will be 8 Kbytes, mapped from 00’C000h

to 00’DFFFh, exactly as in the ST10F269.

Note:

XADRS3 cannot be changed after executing the EINIT instruction.

4.1.3

Software impact for the ST10F272E

On ST10F272E, this register must be programmed by the user before accessing XRAM2 so

that:

●

RGSZ defines a 16 Kbyte window size. RGSZ = 0110b

●

RGSAD defines bits 8 to 19 of the window start address aligned to a 16-Kbyte

boundary (the least significant bits of the field are not relevant).

In the ST10F272E, the XRAM2 cannot be located within page 3 of segment 0. The user can

either:

●

map the XRAM2 from anywhere above address 09’0000h

●

map the XRAM2 in the 16-Kbyte page available in segment 0 in the 00’8000h -

00’BFFFh range.

The desired value should be written in XADRS3 register before enabling XRAM2 in the

SYSCON and XPERCON registers.

Note:

XADRS3 cannot be changed after executing the EINIT instruction.

Example

To map the 16-Kbyte XRAM2 onto page 60 (starting address 0F’0000h, compatible

with the ST10F276E), then XADRS3 must be initialized with the value F006h.

To map the 16-Kbyte XRAM2 onto page 2 (starting address 00’8000h), then XADRS3

must be initialized with the value 0806h.

Variables and PEC transfers

For architecture reasons, the PEC destination and source pointers must be in the segment

0. Therefore, all RAM variables and arrays that are PEC-addressed must be located in RAM

memory available in segment 0 (DPRAM + XRAM1, and XRAM2 if remapped onto page 2).

About Toolchain memory model

A change in the Toolchain configuration is needed to take into account the XRAM2’s new

location. In the ST10F269, all the XRAM is in page 3 and it is then automatically addressed

using DPP3 that points to page 3 (in order to access the DPRAM and the SFR/ESFR). For

the ST10F272, it is necessary to dedicate a DPP to access some of XRAM2.

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