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AN2021 数据表(PDF) 32 Page - STMicroelectronics |
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AN2021 数据表(HTML) 32 Page - STMicroelectronics |
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32 / 39 page ![]() New registers AN2021 32/39 4.4.1 Hardware impact None. 4.4.2 Software impact None. 1CANPAR CAN Parallel Mode Selection 0: CAN2 is mapped on P4.4/P4.7, while CAN1 is mapped on P4.5/P4.6 1: CAN1 and CAN2 are mapped in parallel on P4.5/P4.6. This is effective only if both CAN1 and CAN2 are enabled (bits CAN1EN and CAN2EN set in XPERCON register). If CAN1 is disabled, CAN2 remains on P4.4/P4.7 even if the CANPAR bit is set. 0 ADCMUX Port1L ADC Channels Enable 0: Analog inputs on port P5.y can be converted (default configuration) 1: Analog inputs on port P1.z can be converted. Only 8 channels can be managed Table 18. XMISC register description (continued) Bit Bit name Function |
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