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AN2021 数据表(PDF) 35 Page - STMicroelectronics

部件名 AN2021
功能描述  The ST10F272B and ST10F272E are members of the STMicroelectronics
PDF  39 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

AN2021 数据表(HTML) 35 Page - STMicroelectronics

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AN2021
Electrical characteristics
35/39
Multiplexed bus
Demultiplexed bus
Table 20.
Multiplexed bus timings (ns)
Symbol
Parameter
ST10F269
ST10F272
ST10F269
@fCPU = 40 MHz
ST10F272
@fCPU = 40 MHz
Min
Max
Min
Max
Min
Max
Min
Max
t6 CC
Address setup to
ALE
TCL - 10.5
+ tA
-
TCL - 11 +
tA
-2 + tA
-
1.5 + tA
-
t16 SR
ALE low to valid
data in
-
3 TCL - 19
+ tA + tC
-
3 TCL - 20
+ tA + tC
18.5 + tA +
tC
-
17.5 + tA +
tC
-
t17 SR
Address/Unlatch
ed CS to valid
data in
-
4 TCL - 28
+ 2tA + tC
-
4 TCL - 30
+ 2tA + tC
22 + 2tA +
tC
-
20 + 2tA +
tC
-
t39 SR
Latched CS low
to valid data In
-
3 TCL - 19
+ 2tA + tC
-
3 TCL - 21
+ 2tA + tC
18.5 + 2tA
+ tC
-
16.5 + 2tA
+ tC
-
t44 CC
Address float
after RdCS,
WrCS (with RW
delay)
-0-
1.5
-
0
-
1.5
t45 CC
Address float
after RdCS,
WrCS (no RW
delay)
-
TCL
-
TCL + 1.5
-
12.5
-
14
Table 21.
Demultiplexed bus timings
Symbol
Parameter
ST10F269
ST10F272
ST10F269
@fCPU = 40 MHz
ST10F272
@fCPU =
40 MHz
Min
Max
Min
Max
Min
Max
Min
Max
t6 CC
Address setup to
ALE
TCL -
10.5 + tA
-
TCL - 11
+ tA
-2 + tA
-
1.5 +
tA
-
t80 CC
Address/Unlatched
CS setup to RD,
WR (with RW
delay)
-
2 TCL -
8.5 + 2tA
-
2 TCL -
12.5 + 2tA
16.5 + 2tA
-
12.5 +
2tA
-
t81 CC
Address/Unlatched
CS setup to RD,
WR (no RW delay)
-
TCL - 8.5
+ 2tA
-
TCL - 12
+ 2tA
4 + 2tA
-
0.5 +
2tA
-
t16 SR
ALE low to valid
data in
-
3 TCL - 19
+ tA + tC
-
3 TCL - 20
+ tA + tC
18.5 + tA
+ tC
-
17.5 +
tA + tC
-
t17 SR
Address/Unlatched
CS to valid data in
-
4 TCL - 28
+ 2tA + tC
-
4 TCL - 30
+ 2tA + tC
22 + 2tA +
tC
-
20 +
2tA +
tC
-



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