LTC2410IGN datasheet(9/44 Pages) LINER

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LTC2410

Input Voltage Range

The analog input is truly differential with an absolute/

common mode range for the IN+ and IN– input pins

extending from GND – 0.3V to VCC + 0.3V. Outside

these limits the ESD protection devices begin to turn on

and the errors due to input leakage current increase

rapidly. Within these limits the LTC2410 converts the

bipolar differential input signal, VIN = IN+ – IN–, from

– FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF =

REF+ – REF–. Outside this range the converter indicates the

overrange or the underrange condition using distinct

output codes.

Input signals applied to IN+ and IN– pins may extend by

300mV below ground and above VCC. In order to limit any

fault current, resistors of up to 5k may be added in series

with the IN+ and IN– pins without affecting the perfor-

mance of the device. In the physical layout, it is important

to maintain the parasitic capacitance of the connection

between these series resistors and the corresponding pins

as low as possible; therefore, the resistors should be

located as close as practical to the pins. The effect of the

series resistance on the converter accuracy can be evalu-

ated from the curves presented in the Input Current/

Reference Current sections. In addition, series resistors

will introduce a temperature dependent offset error due to

the input leakage current. A 1nA input leakage current will

develop a 1ppm offset error on a 5k resistor if VREF = 5V.

This error has a very strong temperature dependency.

Output Data Format

The LTC2410 serial output data stream is 32 bits long. The

first 3 bits represent status information indicating the sign

and conversion state. The next 24 bits are the conversion

result, MSB first. The remaining 5 bits are sub LSBs

beyond the 24-bit level that may be included in averaging

or discarded without loss of resolution. The third and

fourth bit together are also used to indicate an underrange

condition (the differential input voltage is below –FS) or an

overrange condition (the differential input voltage is above

+FS).

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 30 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 29 (third output bit) is the conversion result sign indi-

cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this

bit is LOW.

Bit 28 (fourth output bit) is the most significant bit (MSB)

of the result. This bit in conjunction with Bit 29 also

provides the underrange or overrange indication. If both

Bit 29 and Bit 28 are HIGH, the differential input voltage is

above +FS. If both Bit 29 and Bit 28 are LOW, the

differential input voltage is below –FS.

The function of these bits is summarized in Table 1.

Table 1. LTC2410 Status Bits

Bit 31

Bit 30 Bit 29 Bit 28

Input Range

EOC

DMY

SIG

MSB

VIN ≥ 0.5 • VREF

≤ VIN < 0.5 • VREF

–0.5 • VREF ≤ VIN < 0V

VIN < – 0.5 • VREF

Bits 28-5 are the 24-bit conversion result MSB first.

Bit 5 is the least significant bit (LSB).

Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may

be included in averaging or discarded without loss of

resolution.

Data is shifted out of the SDO pin under control of the serial

clock (SCK), see Figure 3. Whenever CS is HIGH, SDO

remains high impedance and any externally generated

SCK clock pulses are ignored by the internal data out shift

In order to shift the conversion result out of the device, CS

must first be driven LOW. EOC is seen at the SDO pin of the

device once CS is pulled LOW. EOC changes real time from

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external

microcontroller. Bit 31 (EOC) can be captured on the first

rising edge of SCK. Bit 30 is shifted out of the device on the

first falling edge of SCK. The final data bit (Bit 0) is shifted

out on the falling edge of the 31st SCK and may be latched

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