LTC2410IGN datasheet(10/44 Pages) LINER

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LTC2410

on the rising edge of the 32nd SCK pulse. On the falling

edge of the 32nd SCK pulse, SDO goes HIGH indicating the

initiation of a new conversion cycle. This bit serves as EOC

(Bit 31) for the next conversion cycle. Table 2 summarizes

the output data format.

As long as the voltage on the IN+ and IN– pins is maintained

within the – 0.3V to (VCC + 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage VIN from –FS = –0.5 • VREF to

+FS = 0.5 • VREF. For differential input voltages greater than

+FS, the conversion result is clamped to the value corre-

sponding to the +FS + 1LSB. For differential input voltages

below –FS, the conversion result is clamped to the value

corresponding to –FS – 1LSB.

Frequency Rejection Selection (FO)

The LTC2410 internal oscillator provides better than 110dB

normal mode rejection at the line frequency and all its

harmonics for 50Hz

±2% or 60Hz ±2%. For 60Hz rejec-

tion, FO should be connected to GND while for 50Hz

rejection the FO pin should be connected to VCC.

The selection of 50Hz or 60Hz rejection can also be made

by driving FO to an appropriate logic level. A selection

change during the sleep or data output states will not

disturb the converter operation. If the selection is made

during the conversion state, the result of the conversion in

progress may be outside specifications but the following

conversions will not be affected.

When a fundamental rejection frequency different from

50Hz or 60Hz is required or when the converter must be

Table 2. LTC2410 Output Data Format

Differential Input Voltage

Bit 31

Bit 30

Bit 29

Bit 28

Bit 27

Bit 26

Bit 25

…

Bit 0

VIN*

EOC

DMY

SIG

MSB

VIN* ≥ 0.5 • VREF**

0110

…

0.5 • VREF** – 1LSB

0101

…

0.25 • VREF**

0101

…

0.25 • VREF** – 1LSB

0100

…

0100

…

–1LSB

0011

…

– 0.25 • VREF**

0011

…

– 0.25 • VREF** – 1LSB

0010

…

– 0.5 • VREF**

0010

…

VIN* < –0.5 • VREF**

0001

…

*The differential input voltage VIN = IN+ – IN–.

**The differential reference voltage VREF = REF+ – REF–.

Figure 3. Output Data Timing

APPLICATIO S I FOR ATIO

MSB

SIG

“0”

BIT 0

BIT 27

BIT 5

LSB24

BIT 28

BIT 29

BIT 30

SDO

SCK

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

2410 F03

Hi-Z

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