LTC2410IGN datasheet(16/44 Pages) LINER

16 / 44 page

LTC2410

APPLICATIO S I FOR ATIO

frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled

HIGH before time tEOCtest, the device remains in the sleep

state. The conversion result is held in the internal static

shift register.

If CS remains LOW longer than tEOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data output cycle begins on

this first rising edge of SCK and concludes after the 32nd

rising edge. Data is shifted out the SDO pin on each falling

edge of SCK. The internally generated serial clock is output

to the SCK pin. This signal may be used to shift the

conversion result into external circuitry. EOC can be

latched on the first rising edge of SCK and the last bit of the

conversion result on the 32nd rising edge of SCK. After the

32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays

HIGH and a new conversion starts.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 32nd rising edge

of SCK, see Figure 9. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. This is useful for systems not requiring

all 32 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. If CS is

pulled HIGH while the converter is driving SCK LOW, the

internal pull-up is not available to restore SCK to a logic

HIGH state. This will cause the device to exit the internal

serial clock mode on the next falling edge of CS. This can

be avoided by adding an external 10k pull-up resistor to

the SCK pin or by never pulling CS HIGH when SCK is LOW.

Whenever SCK is LOW, the LTC2410’s internal pull-up at

pin SCK is disabled. Normally, SCK is not externally driven

if the device is in the internal SCK timing mode. However,

certain applications may require an external driver on SCK.

If this driver goes Hi-Z after outputting a LOW signal, the

LTC2410’s internal pull-up remains disabled. Hence, SCK

remains LOW. On the next falling edge of CS, the device is

switched to the external SCK timing mode. By adding an

external 10k pull-up resistor to SCK, this pin goes HIGH

once the external driver goes Hi-Z. On the next CS falling

edge, the device will remain in the internal SCK timing

mode.

Figure 9. Internal Serial Clock, Reduced Data Output Length

SDO

SCK

(INTERNAL)

>tEOCtest

MSB

SIG

BIT 8

TEST EOC

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

EOC

BIT 31

EOC

BIT 0

SLEEP

DATA OUTPUT

Hi-Z

DATA OUTPUT

CONVERSION

SLEEP

2410 F09

<tEOCtest

VCC

10k

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

VCC

TEST EOC

VCC

REF+

REF–

SCK

IN+

IN–

SDO

GND

214

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

3-WIRE

SPI INTERFACE

µF

2.7V TO 5.5V

LTC2410

LTC2410IGN 数据表(PDF) 16 Page - Linear Technology

LTC2410IGN 数据表(HTML) 16 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载