LTC2410IGN datasheet(12/44 Pages) LINER

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LTC2410

APPLICATIO S I FOR ATIO

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 13) is used to

synchronize the data transfer. Each bit of data is shifted out

the SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is an

output and the LTC2410 creates its own serial clock by

dividing the internal conversion clock by 8. In the External

SCK mode of operation, the SCK pin is used as input. The

internal or external SCK mode is selected on power-up and

then reselected every time a HIGH-to-LOW transition is

detected at the CS pin. If SCK is HIGH or floating at power-

up or during this transition, the converter enters the inter-

nal SCK mode. If SCK is LOW at power-up or during this

transition, the converter enters the external SCK mode.

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 12), provides the

result of the last conversion as a serial bit stream (MSB

first) during the data output state. In addition the SDO pin

is used as an end of conversion indicator during the

conversion and sleep states.

When CS (Pin 11) is HIGH, the SDO driver is switched to

a high impedance state. This allows sharing the serial

interface with other devices. If CS is LOW during the

convert or sleep state, SDO will output EOC. If CS is LOW

during the conversion phase, the EOC bit appears HIGH on

the SDO pin. Once the conversion is complete, EOC goes

LOW. The device remains in the sleep state until the first

rising edge of SCK occurs while CS = LOW.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 11), is used to test the

conversion status and to enable the data output transfer as

described in the previous sections.

In addition, the CS signal can be used to trigger a new

conversion cycle before the entire serial data transfer has

been completed. The LTC2410 will abort any serial data

transfer in progress and start a new conversion cycle

anytime a LOW-to-HIGH transition is detected at the CS

pin after the converter has entered the data output state

(i.e., after the first rising edge of SCK occurs with

CS = LOW).

Finally, CS can be used to control the free-running modes

of operation, see Serial Interface Timing Modes section.

Grounding CS will force the ADC to continuously convert

at the maximum output rate selected by FO. Tying a

capacitor to CS will reduce the output rate and power

dissipation by a factor proportional to the capacitor’s

value, see Figures 12 to 14.

SERIAL INTERFACE TIMING MODES

The LTC2410’s 3-wire interface is SPI and MICROWIRE

compatible. This interface offers several flexible modes of

operation. These include internal/external serial clock,

2- or 3-wire I/O, single cycle conversion and autostart. The

following sections describe each of these serial interface

timing modes in detail. In all these cases, the converter

can use the internal oscillator (FO = LOW or FO = HIGH) or

an external oscillator connected to the FO pin. Refer to

Table 4 for a summary.

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 5.

Table 4. LTC2410 Interface Timing Modes

Conversion

Data

Connection

SCK

Cycle

Output

and

Configuration

Source

Control

Waveforms

External SCK, Single Cycle Conversion

External

CS and SCK

Figures 5, 6

External SCK, 2-Wire I/O

External

SCK

Figure 7

Internal SCK, Single Cycle Conversion

Internal

↓

Figures 8, 9

Internal SCK, 2-Wire I/O, Continuous Conversion

Internal

Continuous

Internal

Figure 10

Internal SCK, Autostart Conversion

Internal

CEXT

Internal

Figure 11

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