LTC2410IGN datasheet(14/44 Pages) LINER

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LTC2410

APPLICATIO S I FOR ATIO

Since CS is tied LOW, the end-of-conversion (EOC) can be

continuously monitored at the SDO pin during the convert

and sleep states. EOC may be used as an interrupt to an

external controller indicating the conversion result is

ready. EOC = 1 while the conversion is in progress and

EOC = 0 once the conversion enters the low power sleep

state. On the falling edge of EOC, the conversion result is

loaded into an internal static shift register. The device

remains in the sleep state until the first rising edge of SCK.

Data is shifted out the SDO pin on each falling edge of SCK

enabling external circuitry to latch data on the rising edge

of SCK. EOC can be latched on the first rising edge of SCK.

On the 32nd falling edge of SCK, SDO goes HIGH (EOC = 1)

indicating a new conversion has begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the

serial clock pin (SCK) must be floating (Hi-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resistor

is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is auto-

matically selected if SCK is not externally driven.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the device is in the sleep state.

When testing EOC, if the conversion is complete (EOC = 0),

the device will exit the sleep state and enter the data output

state if CS remains LOW. In order to prevent the device

from exiting the low power sleep state, CS must be pulled

HIGH before the first rising edge of SCK. In the internal

SCK timing mode, SCK goes HIGH and the device begins

outputting data at time tEOCtest after the falling edge of CS

(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW

during the falling edge of EOC). The value of tEOCtest is 23µs

if the device is using its internal oscillator (F0 = logic LOW

or HIGH). If FO is driven by an external oscillator of

Figure 6. External Serial Clock, Reduced Data Output Length

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

SDO

SCK

(EXTERNAL)

DATA OUTPUT

CONVERSION

SLEEP

TEST EOC

DATA OUTPUT

Hi-Z

CONVERSION

2410 F06

MSB

SIG

BIT 8

BIT 27

BIT 9

BIT 28

BIT 29

BIT 30

EOC

BIT 31

BIT 0

EOC

Hi-Z

VCC

TEST EOC

VCC

REF+

REF–

SCK

IN+

IN–

SDO

GND

214

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

3-WIRE

SPI INTERFACE

µF

2.7V TO 5.5V

LTC2410

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