DM385 datasheet(133/281 Pages) TI

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DM385, DM388

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SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

7.2.7

Standby and Deep Sleep Modes

The device supports Low-Power Standby and Deep-Sleep Modes as described below.

Standby Mode is defined as a state in which:

•

All switchable power domains are in "OFF" state

•

The ARM Cortex-A8 is executing an IDLE loop at its lowest frequency of operation

•

All functional blocks not needed for a given application are clock gated

Deep Sleep Mode is defined to be the same as Standby Mode, with the addition of gating the crystal

oscillator to further eliminate all active power. The device core voltages can be reduced for optimal power

savings.

For detailed instructions on entering and exiting from Standby and Deep Sleep Modes, see the Power,

Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical Reference

Manual.

7.2.8

Supply Sequencing

The device power supplies are organized into five Supply Sequencing Groups:

1. CVDD Core Logic supply (CVDD)

2. All CVDD_x supplies (CVDD_ARM and CVDD_HDVICP)

3. All 1.35-/1.5-/1.8-V DVDD_DDR[0] Supplies (1.35 V for DDR3L, 1.5 V for DDR3, 1.8 V for DDR2)

4. All 1.8-V Supplies (DVDD_x, VDDA_x_1P8, VDDA_1P8)

5. All 3.3-V Supplies (DVDD, DVDD_x, DVDD_C, VDDA_x_3P3)

To ensure proper device operation, a specific power-up and power-down sequence must be followed.

Some TI power-supply devices include features that facilitate these power sequencing requirements — for

example, TI’s TPS659113 integrated PMIC. For more information on TI power supplies and their features,

visit www.ti.com/processorpower.

7.2.8.1

Power-Up Sequence

For proper device operation, the following power-up sequence in Table 7-5 and Figure 7-1 must be

followed.

Table 7-5. Power-Up Sequence Ramping Values

NO.

DESCRIPTION

MIN

MAX

UNIT

1.8 V supplies to 1.35-/1.5-/1.8-V DVDD_DDR[x] supplies

0(1)

DVDD_DDR supplies stable to 3.3 V supplies ramp start

0(2)

1.8 V supplies stable to CVDD, CVDD_x variable supplies

0(1)

ramp start

Master

All supplies valid to power-on-reset (POR high)

4 096

Clocks

(1)

The 1.8 V supplies must be

≥ 1.35-/1.5-/1.8-V DVDD_DDR[x] and CVDD, CVDD_x variable supplies.

(2)

Both 1.8 V and DVDD_DDR[x] supplies must be powered up and stable prior to starting the ramp of the 3.3 V supplies.

Power, Reset, Clocking, and Interrupts

133

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