PIC16LC773 datasheet(37/200 Pages) MICROCHIP

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PIC16C77X

Advance Information

DS30275A-page 37

3.6

Parallel Slave Port

The Parallel Slave Port is implemented on the

40/44-pin devices only.

PORTD operates as an 8-bit wide Parallel Slave Port,

or microprocessor port when control bit PSPMODE

(TRISE<4>) is set. In slave mode it is asynchronously

readable and writable by the external world through RD

control input pin RE0/RD and WR control input pin

RE1/WR.

It can directly interface to an 8-bit microprocessor data

bus. The external microprocessor can read or write the

PORTD latch as an 8-bit latch. Setting bit PSPMODE

enables port pin RE0/RD to be the RD input, RE1/WR

to be the WR input and RE2/CS to be the CS (chip

select) input. For this functionality, the corresponding

data direction bits of the TRISE register (TRISE<2:0>)

must be configured as inputs (set). The configuration

bits, PCFG3:PCFG0 (ADCON1<3:0>) must be config-

ured to make pins RE2:RE0 as digital I/O.

A write to the PSP occurs when both the CS and WR

lines are first detected low. A read from the PSP occurs

when both the CS and RD lines are first detected low.

FIGURE 3-13: PORTD AND PORTE BLOCK

DIAGRAM (PARALLEL SLAVE

PORT)

FIGURE 3-14: PARALLEL SLAVE PORT WRITE WAVEFORMS

Data bus

PORT

RDx

PORT

One bit of PORTD

Set interrupt flag

PSPIF (PIR1<7>)

Read

Chip Select

Write

Note: I/O pin has protection diodes to VDD and VSS.

TTL

IBF

OBF

PSPIF

PORTD<7:0>

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