PIC16LC773 datasheet(57/200 Pages) MICROCHIP

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PIC16C77X

Advance Information

DS30275A-page 57

8.1

SPI Mode

The SPI mode allows 8-bits of data to be synchro-

nously transmitted and received simultaneously. All

four modes of SPI are supported. To accomplish com-

munication, typically three pins are used:

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Serial Clock (SCK)

Additionally, a fourth pin may be used when in a slave

mode of operation:

•Slave Select (SS)

8.1.1

OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master Mode (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data input sample phase

(middle or end of data output time)

• Clock edge

(output data on rising/falling edge of SCK)

• Clock Rate (Master mode only)

• Slave Select Mode (Slave mode only)

Figure 8-4 shows the block diagram of the MSSP mod-

ule when in SPI mode.

FIGURE 8-4:

MSSP BLOCK DIAGRAM

(SPI MODE)

The MSSP consists of a transmit/receive Shift Register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR,

until the received data is ready. Once the 8-bits of data

have been received, that byte is moved to the SSPBUF

Then

the

buffer

full

detect

bit

(SSPSTAT<0>) and the interrupt flag bit SSPIF

(PIR1<3>) are set. This double buffering of the

received data (SSPBUF) allows the next byte to start

reception before reading the data that was just

received. Any write to the SSPBUF register during

transmission/reception of data will be ignored, and the

write collision detect bit WCOL (SSPCON<7>) will be

set. User software must clear the WCOL bit so that it

can be determined if the following write(s) to the SSP-

BUF register completed successfully.

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. Buffer

full bit, BF (SSPSTAT<0>), indicates when the SSP-

BUF has been loaded with the received data (transmis-

sion is complete). When the SSPBUF is read, bit BF is

cleared. This data may be irrelevant if the SPI is only a

transmitter. Generally the MSSP Interrupt is used to

Read

Write

Internal

data bus

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0

shift

clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 output

TOSC

Prescaler

4, 16, 64

Edge

Select

Data to TX/RX in SSPSR

Data direction bit

SMP:CKE

SDI

SDO

SCK

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