PIC16LC773 datasheet(87/200 Pages) MICROCHIP

87 / 200 page

PIC16C77X

Advance Information

DS30275A-page 87

8.2.14

STOP CONDITION TIMING

A stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit PEN (SSPCON2<2>). At the end of a receive/trans-

mit the SCL line is held low after the falling edge of the

ninth clock. When the PEN bit is set, the master will

assert the SDA line low . When the SDA line is sam-

pled low, the baud rate generator is reloaded and

counts down to 0. When the baud rate generator times

out, the SCL pin will be brought high, and one TBRG

(baud rate generator rollover count) later, the SDA pin

will be de-asserted. When the SDA pin is sampled high

while SCL is high, the P bit (SSPSTAT<4>) is set. A

TBRG later the PEN bit is cleared and the SSPIF bit is

set (Figure 8-31).

Whenever the firmware decides to take control of the

bus, it will first determine if the bus is busy by checking

the S and P bits in the SSPSTAT register. If the bus is

busy, then the CPU can be interrupted (notified) when

a Stop bit is detected (i.e. bus is free).

8.2.14.14 WCOL STATUS FLAG

If the user writes the SSPBUF when a STOP sequence

is in progress, then WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

FIGURE 8-31: STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSPCON2

Set PEN

Falling edge of

SCL = 1 for T

BRG, followed by SDA = 1 for TBRG

9th clock

SCL brought high after T

BRG

Note: T

BRG = one baud rate generator period.

BRG

after SDA sampled high. P bit (SSPSTAT<4>) is set

BRG

to setup stop condition.

ACK

BRG

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

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