CF745 datasheet(25/217 Pages) MICROCHIP

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Preliminary

DS30453B-page 25

PIC16C5X

5.0

I/O PORTS

As with any other register, the I/O registers can be

written and read under program control. However, read

instructions (e.g., MOVF PORTB,W) always read the I/O

pins independent of the pin’s input/output modes. On

RESET, all I/O ports are deﬁned as input (inputs are at

hi-impedance) since the I/O control registers (TRISA,

TRISB, TRISC) are all set.

5.1

PORTA

PORTA is a 4-bit I/O register. Only the low order 4 bits

are used (RA3:RA0). Bits 7-4 are unimplemented and

read as '0's.

5.2

PORTB

PORTB is an 8-bit I/O register (PORTB<7:0>).

5.3

PORTC

PORTC is an 8-bit I/O register for PIC16C55s,

PIC16C57s and PIC16CR57s.

PORTC is a general purpose register for PIC16C52,

PIC16C54s, PIC16CR54s, PIC16C56s, PIC16C58s

and PIC16CR58s.

5.4

TRIS Registers

The output driver control registers are loaded with the

contents of the W register by executing the TRIS f

instruction. A '1' from a TRIS register bit puts the

corresponding output driver in a hi-impedance mode.

A '0' puts the contents of the output data latch on the

selected pins, enabling the output buffer.

The TRIS registers are “write-only” and are set (output

drivers disabled) upon RESET.

Note:

A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the external system is holding it low, a

read of the port will indicate that the pin is

low.

5.5

I/O Interfacing

The equivalent circuit for an I/O port pin is shown in

Figure 5-1. All ports may be used for both input and

output operation. For input operations these ports are

non-latching. Any input must be present until read by

an input instruction (e.g., MOVF

PORTB,

). The

outputs are latched and remain unchanged until the

output latch is rewritten. To use a port pin as output,

the corresponding direction control bit (in TRISA,

TRISB) must be cleared (= 0). For use as an input, the

corresponding TRIS bit must be set. Any I/O pin can

be programmed individually as input or output.

FIGURE 5-1:

EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Note 1: I/O pins have protection diodes to VDD and VSS.

Data

Bus

Port

TRIS ‘f’

Data

TRIS

RD Port

VSS

VDD

I/O

pin(1)

Reg

Latch

Reset

TABLE 5-1:

SUMMARY OF PORT REGISTERS

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

N/A

TRIS

I/O control registers (TRISA, TRISB, TRISC)

1111 1111

05h

PORTA

—

RA3

RA2

RA1

RA0

---- xxxx

---- uuuu

06h

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

uuuu uuuu

07h

PORTC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx

uuuu uuuu

Legend: Shaded boxes = unimplemented, read as ‘0’,

–

= unimplemented, read as '0', x = unknown, u = unchanged

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