CF745 datasheet(9/217 Pages) MICROCHIP

9 / 217 page

Preliminary

DS30453B-page 9

PIC16C5X

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC16C5X family can be

attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC16C5X uses a Harvard architecture in

which program and data are accessed on separate

buses. This improves bandwidth over traditional von

Neumann architecture where program and data are

fetched on the same bus. Separating program and

data memory further allows instructions to be sized

differently than the 8-bit wide data word. Instruction

opcodes are 12-bits wide making it possible to have all

single word instructions. A 12-bit wide program

memory access bus fetches a 12-bit instruction in a

single cycle. A two-stage pipeline overlaps fetch and

execution of instructions. Consequently, all instructions

(33) execute in a single cycle (200ns @ 20MHz)

except for program branches.

The PIC16C52 addresses 384 x 12 of program

memory, the PIC16C54s/CR54s and PIC16C55s

address

512 x 12

program

memory,

the

PIC16C56s/CR56s address 1K X 12 of program

memory,

and

the

PIC16C57s/CR57s

and

PIC16C58s/CR58s

address

2K x 12

program

memory. All program memory is internal.

The PIC16C5X can directly or indirectly address its

registers including the program counter are mapped in

the data memory. The PIC16C5X has a highly

orthogonal (symmetrical) instruction set that makes it

possible to carry out any operation on any register

using any addressing mode. This symmetrical nature

and

lack

‘special

optimal

situations’

make

programming with the PIC16C5X simple yet efﬁcient.

In addition, the learning curve is reduced signiﬁcantly.

The PIC16C5X device contains an 8-bit ALU and

working register. The ALU is a general purpose

arithmetic unit. It performs arithmetic and Boolean

functions between data in the working register and any

The ALU is 8-bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the W (working) register. The

other operand is either a ﬁle register or an immediate

constant. In single operand instructions, the operand

is either the W register or a ﬁle register.

The W register is an 8-bit working register used for

ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC),

and Zero (Z) bits in the STATUS register. The C and

DC bits operate as a borrow and digit borrow out bit,

respectively, in subtraction. See the SUBWF and ADDWF

instructions for examples.

A simpliﬁed block diagram is shown in Figure 3-1, with

the corresponding device pins described in Table 3-1.

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