CF745 datasheet(29/217 Pages) MICROCHIP

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Preliminary

DS30453B-page 29

PIC16C5X

6.1

Using Timer0 with an External Clock

When an external clock input is used for Timer0, it

must meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.1.1

EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

T0CKI

with

the

internal

phase

clocks

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-5). Therefore, it is necessary for T0CKI to be

high for at least 2TOSC (and a small RC delay of 20 ns)

and low for at least 2TOSC (and a small RC delay of

20 ns). Refer to the electrical speciﬁcation of the

desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler so that the prescaler output is symmetrical.

For

the

external

clock

meet

the

sampling

requirement, the ripple counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4TOSC (and a small RC delay of

40 ns) divided by the prescaler value. The only

requirement on T0CKI high and low time is that they

do not violate the minimum pulse width requirement of

10 ns. Refer to parameters 40, 41 and 42 in the

electrical speciﬁcation of the desired device.

6.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 6-5 shows the

delay from the external clock edge to the timer

incrementing.

FIGURE 6-5:

TIMER0 TIMING WITH EXTERNAL CLOCK

Increment Timer0 (Q4)

External Clock Input or

Q1 Q2 Q3 Q4

Timer0

T0 + 1

T0 + 2

Small pulse

misses sampling

External Clock/Prescaler

Output After Sampling

(3)

Note 1:

Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input =

± 4Tosc max.

External clock if no prescaler selected, Prescaler output otherwise.

The arrows indicate the points in time where sampling occurs.

Prescaler Output (2)

(1)

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