A25LS512A Series

(November, 2014, Version 1.1)

6

AMIC Technology Corp.

Table 1. Protected Area Sizes

A25LS512A

Status Register Content

Memory Content

BP2 Bit

BP1 Bit

BP0 Bit

Protected Area

Unprotected Area

X

0

0

None

All block

1

X

X

1

All block

None

X

1

X

All block

None

Note: 1. The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0