A25LS512A Series

(November, 2014, Version 1.1)

13

AMIC Technology Corp.

Table 5. Protection Modes

Memory Content

W

Signal

SRWD

Bit

Mode

Write Protection of the Status

Register

Protected Area

1

Unprotected Area

1

1

0

0

0

1

1

Software

Protected

(SPM)

Status Register is Writable (if the

WREN instruction has set the WEL

bit).

The values in the SRWD, BP2, BP1,

and BP0 bits can be changed

Protected against Page

Program, Sector Erase,

Block Erase, and Chip

Erase

Ready to accept Page

Program, Sector Erase,

and Block Erase

instructions

0

1

Hardware

Protected

(HPM)

Status Register is Hardware write

protected.

The values in the SRWD, BP2, BP1,

and BP0 bits cannot be changed

Protected against Page

Program, Sector Erase,

Block Erase, and Chip

Erase

Ready to accept Page

Program, Sector Erase,

and Block Erase

instructions

Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.

The protection features of the device are summarized in Table

5.

When the Status Register Write Disable (SRWD) bit of the

Status Register is 0 (its initial delivery state), it is possible to

write to the Status Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction, regardless of the whether Write Protect

(

When the Status Register Write Disable (SRWD) bit of the

Status Register is set to 1, two cases need to be considered,

depending on the state of Write Protect (

­

If Write Protect (

to the Status Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write

Enable (WREN) instruction.

­

If Write Protect (W) is driven Low, it is not possible to

write to the Status Register even if the Write Enable Latch

(WEL) bit has previously been set by a Write Enable

(WREN) instruction. (Attempts to write to the Status

Register are rejected, and are not accepted for execution).

As a consequence, all the data bytes in the memory area

that are software protected (SPM) by the Block Protect

(BP2, BP1, BP0) bits of the Status Register, are also

hardware protected against data modification.

Regardless of the order of the two events, the Hardware

Protected Mode (HPM) can be entered:

­

by setting the Status Register Write Disable (SRWD) bit

after driving Write Protect (

­

or by driving Write Protect (

Status Register Write Disable (SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM)

once entered is to pull Write Protect (

If Write Protect (

Protected Mode (HPM) can never be activated, and only the

Software Protected Mode (SPM), using the Block Protect

(BP2, BP1, BP0) bits of the Status Register, can be used.