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A25LS512A 数据表(PDF) 33 Page - AMIC Technology

部件名 A25LS512A
功能描述  512Kbit Low Voltage, Serial Flash Memory
PDF  43 Pages
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制造商  AMICC [AMIC Technology]
网页  http://www.amictechnology.com
标志 AMICC - AMIC Technology

A25LS512A 数据表(HTML) 33 Page - AMIC Technology

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A25LS512A Series
(November, 2014, Version 1.1)
32
AMIC Technology Corp.
Table 15. AC Characteristics
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
fC
fC
Clock Frequency for the following instructions: FAST_READ,
PP, SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR
(2.7V~3.6V) / (3.0V~3.6V)
D.C.
80/100
MHz
fR
Clock Frequency for READ instructions
D.C.
66
MHz
tCH
1
tCLH
Clock High Time
6
ns
tCL
1
tCLL
Clock Low Time
5
ns
tCLCH
2
Clock Rise Time
3 (peak to peak)
0.1
V/ns
tCHCL
2
Clock Fall Time
3 (peak to peak)
0.1
V/ns
tSLCH
tCSS
S Active Setup Time (relative to C)
5
ns
tCHSL
S Not Active Hold Time (relative to C)
5
ns
tDVCH
tDSU
Data In Setup Time
5
ns
tCHDX
tDH
Data In Hold Time
5
ns
tCHSH
S Active Hold Time (relative to C)
5
ns
tSHCH
S Not Active Setup Time (relative to C)
5
ns
tSHSL
tCSH
S Deselect Time
100
ns
tSHQZ
2
tDIS
Output Disable Time
9
ns
tCLQV
tV
Clock Low to Output Valid
9
ns
tCLQX
tHO
Output Hold Time
0
ns
tHLCH
HOLD Setup Time (relative to C)
5
ns
tCHHH
HOLD Hold Time (relative to C)
5
ns
tHHCH
HOLD Setup Time (relative to C)
5
ns
tCHHL
HOLD Hold Time (relative to C)
5
ns
tHHQX
2
tLZ
HOLD to Output Low-Z
8
ns
tHLQZ
2
tHZ
HOLD to Output High-Z
8
ns
tWHSL
4
Write Protect Setup Time
20
ns
tSHWL
4
Write Protect Hold Time
100
ns
tDP
2
S High to Deep Power-down Mode
3
µs
tRES1
2
S High to Standby Mode without Electronic Signature Read
30
µs
tRES2
2
S High to Standby Mode with Electronic Signature Read
30
µs
tW
Write Status Register Cycle Time
5
15
ms
tpp
Page Program Cycle Time
2
3
ms
tSE
Sector Erase Cycle Time
0.2
0.24
s
tBE
Block Erase Cycle Time
0.5
1.3
s
tCE
Chip Erase Cycle Time of A25LS512A
0.5
1.3
s
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.



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