 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
A25LS512A 数据表(PDF) 10 Page - AMIC Technology |
|
|
|||||||||||||||||||||||||||||
A25LS512A 数据表(HTML) 10 Page - AMIC Technology |
|
|
10 / 43 page  A25LS512A Series (November, 2014, Version 1.1) 9 AMIC Technology Corp. INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (DIO) is sampled on the first rising edge of Serial Clock (C) after Chip Select ( S ) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (DIO), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 3. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, Read Device Identification and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select ( S ) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select ( S ) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select ( S ) must driven High when the number of clock pulses after Chip Select ( S ) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. Table 3. Instruction Set Instruction Description One-byte Instruction Code Address Bytes Dummy Bytes Data Bytes WREN Write Enable 0000 0110 06h 0 0 0 WRDI Write Disable 0000 0100 04h 0 0 0 RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞ WRSR Write Status Register 0000 0001 01h 0 0 1 READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞ FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞ FAST_READ_DUAL _OUTPUT Read Data Bytes at Higher Speed by Dual Output (1) 00111011 3Bh 3 1 1 to ∞ FAST_READ_DUAL _INPUT-OUTPUT Read Data Bytes at Higher Speed by Dual Input and Dual Output (1) 10111011 BBh 3 (2) 1 (2) 1 to ∞ PP Page Program 0000 0010 02h 3 0 1 to 256 SE Sector Erase 0010 0000 20h 3 0 0 BE Block Erase 1101 1000 D8h 3 0 0 CE Chip Erase 1100 0111 C7h 0 0 0 DP Deep Power-down 1011 1001 B9h 0 0 0 RDID Read Device Identification 1001 1111 9Fh 0 0 1 to ∞ REMS Read Electronic Manufacturer & Device Identification 1001 0000 90h 1 (3) 2 1 to ∞ Release from Deep Power-down, and Read Electronic Signature 0 3 1 to ∞ RES Release from Deep Power-down 1010 1011 ABh 0 0 0 Note: (1) DIO = (D6, D4, D2, D0) DO = (D7, D5, D3, D1) (2) Dual Input, DIO = (A22, A20, A18, ………, A6, A4, A2, A0) DO = (A23, A21, A19, …….., A7, A5, A3, A1) (3) ADD= (00h) will output manufacturer’s ID first and ADD=(01h) will output device ID first |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
