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VP310 数据表(PDF) 11 Page - Mitel Networks Corporation

部件名 VP310
功能描述  Satellite Channel Decoder
PDF  31 Pages
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制造商  MITEL [Mitel Networks Corporation]
网页  http://www.mitel.com
标志 MITEL - Mitel Networks Corporation

VP310 数据表(HTML) 11 Page - Mitel Networks Corporation

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VP310
PRELIMINARY DATA
11
1.4.5 The Energy Dispersal (de-scrambler) block, DVB only
Before Reed Solomon encoding in the DVB transmission system, the MPEG2 data stream is
randomised using the configuration shown in Figure 9 below. This is a Pseudo Random Binary
Sequence (PRBS) generator, with the polynomial:
1 + X14 + X15
The PRBS registers are loaded with the initialisation sequence as shown, at the start of the first
transport packet in a group of eight packets. This point is indicated by the inverted sync byte
B8hex. The normal DVB sync byte is 47hex. The data starting with the first byte after the sync byte
is randomised by exclusive-ORing data bits with the PRBS. (The sync bytes themselves are not
randomised).
In the decoder, the process of de-randomising or de-scrambling the data is exactly the same as
described above. The de-scrambler also inverts the sync byte B8hex so that all MPEG output
packets have the same synch byte 47hex.
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
10
010
1
010
0000
00
Initialisation sequence
XOR
Figure 9. DVB Energy dispersal conceptual diagram.
1.4.6 Output stage
Transport stream can be output in a byte-serial or bit-serial mode. The output interface consists
of an 8-bit output, output clock, a packet validation level, a packet start pulse and a block error
indicator.
The output clock rate depends on the Symbol rate, QPSK/BPSK choice, convolutional (Viterbi)
coding rate, DVB/DSS choice and byte-parallel or bit-serial output mode. This rate is computed
by VP310 to be very close to the minimum required to output packet data without packet overlap.
Furthermore, the packets at the output of VP310 are as evenly spaced as possible to minimise
packet position movement in the transport layer. The maximum movement in the packet
synchronisation byte position is limited to
± one output clock period.



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