VP310

PRELIMINARY DATA

2

Overview

The VP310 is a QPSK/BPSK 1 to 45MBaud demodulator and channel decoder

for digital satellite television transmissions compliant to both DVB-S and DSS

standards and other systems, such as LMDS, that use the same architecture.

A Command Driven Control (CDC) system is provided making the VP310 very

simple to program. After the tuner has been programmed to the required

frequency, to acquire a DVB transmission, the VP310 requires a minimum of

five registers to be written, see Figure 15 on page 19. Activity flow diagrams for

initialisation and basic channel change are included in section 2.

The VP310 provides a monitor of Bit Error Rate after the QPSK module and

also after the Viterbi module.

For receiver installation, a high speed scan or ‘blind search’ mode is available.

This allows all signals from a given satellite to be evaluated for frequency,

symbol rate and convolutional coding scheme.

Dual ADC

Timing recovery

Matched filter

Phase recovery

I²C

Interface

DVB

DSS

FEC

Analog

AGC

control

Acquisition

Control

Clock Generation

MPEG/

DSS

Packets

Bus I/O

Q I/P

I I/P

De-rotator

Decimation

Filteriing

Figure 1. VP310 Functional Block Diagram.