VP310

PRELIMINARY DATA

24

3. VP310 register map

RADD is a virtual register with no address containing the address of the register to be accessed.

It is written immediately after the I²C write address.

NAME

ADR

B7

B6

B5

B4

B3

B2

B1

B0

DEF

hex

RADD

N/A

IAI

AD6

AD5

AD4

AD3

AD2

AD1

AD0

-

3.1 Write / Read register map

NAME

ADR

B7

B6

B5

B4

B3

B2

B1

B0

DEF

hex

GPP_CTRL

20

Reserved I2C_PAS

GPP_DIR[2:0]

GPP_PIN[2:0]

20

RESET

21

FR_310

PR_310

FR_QP

PR_QP

FR_VIT

PR_VIT

PR_BA

PR_DS

00

DISEQC_MODE

22

Reserved

HV

DISEQC instruction length

22kHz mode

00

SYM_RATE H

23

SEARCH Reserved

SYM_RATE[13:8] in MBaud (high byte)

1B

SYM_RATE L

24

SYM_RATE[7:0] in MBaud (low byte)

80

VIT_MODE

25

Reserved V_IQ_SP CR 7/8

CR 6/7

CR 5/6

CR 3/4

CR 2/3

CR 1/2

44

QPSK_CTRL

26

Reserved Q_IQ_SP Reserved Reserved Reserved AFC_M Reserved ROLL_20

00

GO

27

Reserved

GO

00

IE_QPSK H

28

IE_QPSK[23:16] Interrupt enable QPSK (high byte)

00

IE_QPSK M

29

IE_QPSK[15:8] Interrupt enable QPSK (middle byte)

00

IE_QPSK L

30

IE_QPSK [7:0] Interrupt enable QPSK (low byte)

00

IE_FEC

31

IE_FEC[7:0] Interrupt enable FEC

00

QPSK_STAT_EN

32

QPSK_STAT_EN[7:0] Enable various QPSK outputs on STATUS pin

00

FEC_STAT_EN

33

FEC_STAT_EN[3:0] Enable various FEC outputs on STATUS pin

04

SYS_CLK

34

SYS_CLK[7:0] - System clock frequency x2 in MHz

00

DISEQC_RATIO

35

DISEQC_RATIO[7:0]

00

DISEQC_INSTR

36

DISEQC Instruction [7:0]

00

FR_LIM

37

Reserved

FR_LIM[6:0] - Freq. Limit in MHz

30

FR_OFF

38

FR_OFF[7:0] - Freq. Offset in MHz

00

AGC_CTRL

39

Reserved Reserved

AGC_SD[1:0]

AGC_BW[2:0]

AGC_SL

26

AGC_REF

41

AGC_REF[7:0] AGC reference level

67

OP_CTRL

96

Reserved BKERIV MCLKIV EN_TEI

BSO

BA_LK[2:0]

33

MON_CTRL

103

MON_CTRL[7:0] Monitor control

00

CONFIG

127

310_EN

DSS_B

DSS_A

BPSK

PLL_FACTOR[1:0] CRYS15 ADCEXT

08