VP310

PRELIMINARY DATA

4

PLEASE NOTE: This manual has the following convention:

All numerical values are shown as decimal numbers, unless otherwise defined.

1. FUNCTIONAL DESCRIPTION

1.1 Introduction

VP310 is a single-chip variable rate digital QPSK/BPSK satellite demodulator and channel

decoder. The VP310 accepts base-band in-phase and quadrature analog signals and delivers an

MPEG or DSS packet data stream. Digital filtering in VP310 removes the need for any external

anti-alias filtering for all symbol rates from 1 to 45Mbaud. Frequency, timing and carrier phase

recovery are all digital and the only feed-back to the analog front-end is for automatic gain

control. The digital phase recovery loop enables very fine bandwidth control that is needed to

overcome performance degradation due to phase and thermal noise.

All acquisition algorithms are built into the VP310 controller. The VP310 can be operated in a

Command Driven Control (CDC) mode by specifying the Symbol rate and Viterbi code rate.

There is also a provision for a search for unknown Symbol rates and Viterbi code rates.

1.2 Analog-to-Digital Converter

The VP310 contains dual 6-bit A/D converters which each sample a 1.0Vpp single-ended analog

input at up to 90MHz. The fixed rate sampling clock is provided on-chip using a programmable

PLL needing only a low cost 10 to 15MHz crystal. Different crystal frequencies can be combined

with different PLL ratios, depending on the maximum symbol rate, allowing a flexible approach to

clock generation.

1.3 QPSK Demodulator

The demodulator in the VP310 consists of signal amplitude offset compensation, frequency offset

compensation, decimation filtering, carrier recovery, symbol recovery and matched filtering.

The decimation filters give continuous operation from 2Mbits/s to 90Mbits/s allowing one receiver

to cover the needs of the consumer market as well as the single carrier per channel (SCPC)

market with the same components without compromising performance, that is, the channel

reception is within 0.5dB from theory. For a given Symbol rate, control algorithms on the chip

detect the number of decimation stages needed and switch them in automatically.

The frequency offset compensation circuitry is capable of tracking out up to ± 15MHz frequency

offset. This allows the system to cope with relatively large frequency uncertainties introduced by

the Low Noise Block (LNB). Full control of the LNB is provided by the DiSEqC outputs from the

VP310. Horizontal / Vertical polarisation and an instruction modulated 22kHz signal are available

under register control. All DiSEqC v1.1 functions are implemented on the VP310.