VP310

PRELIMINARY DATA

7

VIT_ERRPER[23:0]

DATA BITS

ERROR

COUNT

VIT_ERRCNT[23:0]

0

0

IRQ

Figure 3. Viterbi error count measurement.

Figure 3 above shows the bit errors rising until the maximum programmed value of

VIT_ERRPER[23:0] is reached, when an interrupt is generated on the IRQ line to advise the

host microprocessor that a new value of bit error count has been loaded into the

VIT_ERRCNT[23:0] register. The IRQ line will go high when the IE_FEC register is read by the

host microprocessor.

VIT_ERRCNT[23:0] VIT_ERRPER[23:0]

The error count may be expressed as a ratio:

VIT_ERRCNT[23:0]

VIT_ERRPER[23:0] * 4

1.4.1.2 Viterbi error count coarse indication

To assist in the process of aligning the receiver dish aerial, a coarse indication of the number of

bit errors being received can be provided by monitoring the STATUS line with the following set up

conditions.

The frequency of the output waveform will be a function of the bit error count (triggering the

maximum value programmed into the VIT_MAXERR[7:0] register and the dish alignment on the

satellite. This VIT_MAXERR mode is enabled by setting the FEC_STAT_EN register bit B0.

Figure 4 on page 8 shows the bit errors rising to the maximum value programmed and triggering

a change of state on the STATUS line.

The output signal will be in the audio frequency range.