USB3503 datasheet(4/73 Pages) MICROCHIP

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USB3503

DS00001584B-page 4

 2011-2015 Microchip Technology Inc.

1.0

GENERAL DESCRIPTION

The USB3503 is a low-power, USB 2.0 hub controller with HSIC upstream connectivity and three USB 2.0 downtream

ports. The USB3503 operates as a hi-speed hub and supports low-speed, full-speed, and hi-speed downstream devices

on all of the enabled downstream ports.

The USB3503 has been specifically optimized for mobile embedded applications. The pin-count has been reduced by

optimizing the USB3503 for mobile battery-powered embedded systems where power consumption, small package

size, and minimal BOM are critical design requirements. Standby mode power has been minimized. Instead of a dedi-

cated crystal, reference clock inputs are aligned to mobile applications. Flexible integrated power regulators ease inte-

gration into battery powered devices. All required resistors on the USB ports are integrated into the hub. This includes

all series termination resistors on D+ and D– pins and all required pull-down resistors on D+ and D– pins.

The USB3503 includes programmable features such as:

MultiTRAKTM Technology, which utilizes a dedicated Transaction Translator (TT) per port to maintain consistent full-

speed data throughput regardless of the number of active downstream connections. MultiTRAKTM outperforms conven-

tional USB 2.0 hubs with a single TT in USB full-speed data transfers.

PortMap, which provides flexible port mapping and disable sequences. The downstream ports of a USB3503 hub can

be reordered or disabled in any sequence to support multiple platform designs with minimum effort. For any port that is

disabled, the USB3503 hub controllers automatically reorder the remaining ports to match the USB host controller’s port

numbering scheme.

PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment

of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the

PCB.

PHYBoost, which provides programmable levels of Hi-Speed USB signal drive

strength in the downstream port transceivers. PHYBoost attempts to restore USB sig-

nal integrity in a compromised system environment. The graphic on the right shows

an example of Hi-Speed USB eye diagrams before and after PHYBoost signal integ-

rity restoration.

VariSense, which controls the USB receiver sensitivity enabling programmable lev-

els of USB signal receive sensitivity. This capability allows operation in a sub-optimal

system environment, such as when a captive USB cable is used.

1.1

Customer Selectable Features

A default configuration is available in the USB3503 following a reset. This configuration may be sufficient for most appli-

cations. The USB3503 hub may also be configured by an external microcontroller. When using the microcontroller inter-

face, the hub appears as an I2C slave device.

The USB3503 hub supports customer selectable features including:

• Optional customer configuration via I2C.

• Supports compound devices on a port-by-port basis.

• Customizable vendor ID, product ID, and device ID.

• Configurable downstream port power-on time reported to the host.

• Supports indication of the maximum current that the hub consumes from the USB upstream port.

• Supports Indication of the maximum current required for the hub controller.

• Configurable as a either a Self-Powered or Bus-Powered Hub

• Supports custom string descriptors (up to 30 characters):

- Product string

- Manufacturer string

- Serial number string

• When available, I2C configurable options for default configuration may include:

- Downstream ports as non-removable ports

- Downstream ports as disabled ports

- USB signal drive strength

- USB receiver sensitivity

- USB differential pair pin location

USB3503 数据表(PDF) 4 Page - Microchip Technology

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