USB3503 datasheet(19/73 Pages) MICROCHIP

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DS00001584B-page 19

USB3503

5.0

CONFIGURATION OPTIONS

5.1

Hub Configuration Options

The Hub supports a number of features (some are mutually exclusive), and must be configured in order to correctly func-

tion when attached to a USB host controller. There are two principal ways to configure the hub: by writing to configuration

registers using the serial slave port, or by internal default settings. Any configuration registers which are not written by

the serial slave retain their default settings.

5.1.1

MULTI/SINGLE TT

The USB 2.0 Hub is fully specification compliant to the Universal Serial Bus Specification Revision 2.0 April 27,2000

(12/7/2000 and 5/28/2002 Errata). Please reference Chapter 11 (Hub Specification) for general details regarding Hub

operation and functionality.

For performance reasons, the Hub provides 1 Transaction Translator (TT) per port (defined as Multi-TT configuration),

and each TT has 1512 bytes of periodic buffer space and 272 Bytes of non- periodic buffer space (divided into 4 non-

periodic buffers per TT), for a total of 1784 bytes of buffer space for each Transaction Translator.

When configured as a Single-TT Hub (required by USB 2.0 Specification), the Single Transaction Translator will have

1512 bytes of periodic buffer space and 272 bytes of non-periodic buffer space (divided into 4 non-periodic buffers per

TT), for a total of 1784 bytes of buffer space for the entire Transaction Translator. Each Transaction Translator’s buf-

fer is divided as shown in Table 5-1, "Transaction Translator Buffer Chart".

5.2

Default Serial Interface Register Memory Map

The Serial Interface Registers are used to customize the USB3503 for specific applications. Reserved registers or

reserved bits within a defined register should not be written to non-default values or undefined behavior may result.

TABLE 5-1:

TRANSACTION TRANSLATOR BUFFER CHART

Periodic Start-Split Descriptors

256 Bytes

Periodic Start-Split Data

752 Bytes

Periodic Complete-Split Descriptors

128 Bytes

Periodic Complete-Split Data

376 Bytes

Non-Periodic Descriptors

16 Bytes

Non-Periodic Data

256 Bytes

Total for each Transaction Translator

1784 Bytes

TABLE 5-2:

SERIAL INTERFACE REGISTERS

REG

ADDR

R/W

Abbreviation

Section

00h

R/W

VID LSB

VIDL

5.3.1, page 21

01h

R/W

VID MSB

VIDM

5.3.2, page 21

02h

R/W

PID LSB

PIDL

5.3.3, page 21

03h

R/W

PID MSB

PIDM

5.3.4, page 21

04h

R/W

DID LSB

DIDL

5.3.5, page 21

05h

R/W

DID MSB

DIDM

5.3.6, page 21

06h

R/W

Config Data Byte 1

CFG1

5.3.7, page 22

07h

R/W

Config Data Byte 2

CFG2

5.3.8, page 23

08h

R/W

Config Data Byte 3

CFG3

5.3.9, page 23

09h

R/W

Non-Removable Devices

NRD

5.3.10, page 24

0Ah

R/W

Port Disable (Self)

PDS

5.3.11, page 24

0Bh

R/W

Port Disable (Bus)

PDB

5.3.12, page 25

0Ch

R/W

Max Power (Self)

MAXPS

5.3.13, page 25

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