USB3503 datasheet(17/73 Pages) MICROCHIP

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DS00001584B-page 17

USB3503

4.2

Standby Mode

Standby Mode provides a very low power state for maximum power efficiency when no signaling is required. This is the

lowest power state. In Standby Mode all internal regulators are powered off, the PLL is not running, and core logic is

powered down in order to reduce power. Because core logic is powered off, no configuration settings are retained in this

mode and must be re-initialized after RESET_N is negated high.

4.2.1

EXTERNAL HARDWARE RESET_N

A valid hardware reset is defined as an assertion of RESET_N low for a minimum of 100us after all power supplies are

within operating range. While reset is asserted, the Hub (and its associated external circuitry) enters STANDBY MODE

and consumes extremely low current as defined in Table 10-3 and Table 10-4.

Assertion of RESET_N (external pin) causes the following:

• All downstream ports are disabled.

• All transactions immediately terminate; no states are saved.

• All internal registers return to the default state.

• The PLL is halted.

After RESET_N is negated high in the Hub.Init stage, the Hub reads customer-specific data from the ROM.

4.3

Hub Mode

Hub Mode provides functions of configuration and high speed USB hub operation including connection and communi-

cation. Upon entering Hub Mode and initializing internal logic, the device passes through several sequential stages

based on a fixed time interval.

4.3.1

HUB INITIALIZATION STAGE (HUB.INIT)

The first stage is the initialization stage and occurs when Hub mode is entered based on the conditions in Table 4-1. In

this stage the 1.2V regulator is enabled and stabilizes, internal logic is reset, and the PLL locks if a valid REFCLK is

supplied. Configuration registers are initialized to their default state and REF_SEL[1:0] input values are latched. The

USB3503 will complete initialization and automatically enter the next stage after Thubinit. Because the digital logic within

the device is not yet stable, no communication with the device using the serial port is possible. Configuration registers

are initialized to their default state.

4.3.2

HUB WAIT REFCLK STAGE (HUB.WAITREF)

During this stage the serial port is not functional.

If the reference clock is provided before entering hub mode, the USB3503 will transition to the Hub Configuration stage

without pausing in the Hub Wait RefClk stage. Otherwise, the USB3503 will transition to the Hub configuration stage

once a valid reference clock is supplied and the PLL has locked.

4.3.3

HUB CONFIGURATION STAGE (HUB.CONFIG)

In this stage, the SOC has an opportunity to control the configuration of the USB3503 and modify any of the default

configuration settings specified in the integrated ROM. These settings include USB device descriptors, port electrical

settings such as PHY BOOST, and control features. The SOC implements the changes using the serial slave port inter-

face to write configuration & control registers.

See Section 5.3.29, "Register E7h: Serial Port Interlock Control - SP_ILOCK," on page 29 for definition of SP_ILOCK

the bit is not written by the serial port, then the USB3503 completes configuration without any I2C intervention.

If the SP_ILOCK.config_n bit has its default negated high or the SOC negates the bit high using the serial port during

Thubconfig, the USB3503 will remain in the Hub Configuration Stage indefinitely. This will allow the SOC to update other

configuration and control registers without any remaining time-out restrictions. Once the SP_ILOCK.config_n bit is

asserted low by the SOC the device will transition to the next stage.

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