 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADS5294IPFPR 数据表(PDF) 16 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
ADS5294IPFPR 数据表(HTML) 16 Page - Texas Instruments |
|
|
16 / 81 page  ADS5294 SLAS776D – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com 8.12 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter Enabled See (1) (2) (3) ADC CLK Frequency (MSPS) Set-up Time (tsu), ns Hold Time (tH), ns tPROG = (6 / 7) × T + tdelay, ns (4) Zero-Crossing of LCLKP to Data Valid to Zero- tPROG = delay from input clock zero-cross Data Becoming Invalid Crossing of LCLKP rising edge to frame clock zero cross (rising Fs = 1 / T (both edges) edge) (both edges) MIN TYP MAX MIN TYP MAX MIN TYP MAX 80 0.43 0.54 7.5 9 10.5 60 0.54 0.9 7.5 9 10.5 40 1.1 1.45 7.5 9 10.5 (1) Bit clock and Frame clock jitter has been included in the Set-up and hold timing. (2) The LVDS timing depends on the state of the internal PLL. Use Table 3 to configure the PLL when decimation by two is enabled.. (3) For any given ADC input clock frequency, TI recommends to use the highest PLL state to get the best set-up time. The timing numbers are specified under this condition. For example, for a 40-MSPS input clock frequency, use PLL state 3 to get set-up time ≥ 1.1 ns. PLL state 2 can also be used at 40 MSPS, however, the set-up time degrades by 100 to 200 ps (while the hold time improves by a similar amount). (4) Values below correspond to tdelay, not tPROG 8.13 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 4 Filter Enabled See (1) (2) (3) ADC CLK Frequency (MSPS) Set-up Time (tsu), ns Hold Time (tH), ns tPROG = (8 / 7) × T + tdelay, ns (4) Zero-Crossing of LCLKP to Data Valid to Zero- tPROG = delay from input clock zero-cross Data Becoming Invalid Crossing of LCLKP rising edge to frame clock zero cross (rising Fs = 1 / T (both edges) edge) (both edges) MIN TYP MAX MIN TYP MAX MIN TYP MAX 80 1 1.5 7.5 9 10.5 60 1.7 1.7 7.5 9 10.5 (1) Bit clock and Frame clock jitter has been included in the Set-up and hold timing. (2) The LVDS timing depends on the state of the internal PLL. Use Table 4 to configure the PLL when decimation by 4 is enabled (3) For any given ADC input clock frequency, TI recommends to use the highest PLL state to get best set-up time. The timing numbers are specified under this condition. (4) Values below correspond to tdelay, not tPROG 8.14 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter Enabled See (1) (2) (3) ADC CLK Frequency (MSPS) Set-up Time (tsu), ns Hold Time (tH), ns tPROG = (5 / 7) × T + tdelay, ns (4) Zero-Crossing of LCLKP to Data Valid to Zero- tPROG = delay from Input clock zero-cross Data Becoming Invalid Crossing of LCLKP rising edge to frame clock zero cross (rising Fs = 1 / T (both edges) edge) (both edges) MIN TYP MAX MIN TYP MAX MIN TYP MAX 80 2.9 3.2 7.5 9 10.5 (1) Bit clock and Frame clock jitter has been included in the Set-up and hold timing. (2) The LVDS timing depends on the state of the internal PLL. Use Table 5 to configure the PLL when decimation by 8 is enabled (3) For any given ADC input clock frequency, TI recommends using the highest PLL state to get best set-up time. The timing numbers are specified under this condition. (4) Values below correspond to tdelay, not tPROG 16 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: ADS5294 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
