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ADS5294IPFPR 数据表(PDF) 46 Page - Texas Instruments |
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ADS5294IPFPR 数据表(HTML) 46 Page - Texas Instruments |
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46 / 81 page ![]() ADS5294 SLAS776D – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com 9.6.1 Description Of Serial Registers 9.6.1.1 Power-Down Modes Table 7. Power-Down Mode Register ADDR. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME (HEX) 0F X X X X X X X X PDN_CH<8:1> X PDN_PARTIAL X PDN_COMPLETE X PDN_PIN_CFG Each of the eight channels can be individually powered down. PDN_CH<N> controls the power-down mode for ADC channel <N>. In addition to channel-specific power-down, the ADS5294 also has two global power-down modes: 1. The partial power-down mode partially powers down the chip. Recovery time from the partial power-down mode is about 10 µs provided that the clock has been running for at least 50 µs before exiting this mode. 2. The complete power-down mode completely powers down the chip This mode involves a much longer recovery time 100 µs. In addition to programming the chip in either of these two power-down modes (through either the PDN_PARTIAL or PDN_COMPLETE bits), the PD pin itself can be configured as either a partial power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG=0 (default), when the PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG=1, when the PD pin is high, the device enters partial power-down mode. 9.6.1.2 Low Frequency Noise Suppression Mode Table 8. Low Frequency Noise Suppression Mode Register ADDR. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME (HEX) 14 X X X X X X X X LFNS_CH<8:1> The low-frequency noise suppression mode is useful in applications where good noise performance is desired in the frequency band of 0 to 1 MHz (around DC). Setting this mode shifts the low-frequency noise of the ADS5294 to approximately Fs / 2, thereby, moving the noise floor around DC to a much lower value. LFNS_CH<8:1> enables this mode individually for each channel. See Figure 38 and Figure 39. 9.6.1.3 Analog Input Invert Table 9. Analog Input Invert Register ADDR. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME (HEX) 24 X X X X X X X X INVERT_CH<8:1> 46 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: ADS5294 |
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