14-Channel

Analog

Multiplexer

Reference CTRL

12-to-1

Data

Selector

and Driver

Control Logic

and I/O

Counters

Input Address

Register

4

12

4

REF +

REF –

DATA

OUT

DATA IN

I/O CLOCK

CS

3

EOC

17

15

18

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

1

2

3

4

5

6

7

8

9

11

12

14

13

19

Low Power

12-Bit

SAR ADC

Sample

and Hold

Output Data

Register

12

16

20

VCC

10

GND

Internal OSC

Self Test

TLV2553

SLAS354C – SEPTEMBER 2001 – REVISED SEPTEMBER 2015

www.ti.com

8 Detailed Description

8.1 Overview

Initially, with chip select (CS) high, I/O CLOCK and DATA IN are disabled and DATA OUT is in the high-

impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA IN and

removes DATA OUT from the high-impedance state. The input data is an 8–bit data stream consisting of a 4-bit

address or command (D7–D4) and a 4-bit configuration data (D3–D0). Configuration register 1, CFGR1, which

controls output data format configuration, consists of a 2-bit data length select (D3–D2), an output MSB or LSB

first bit (D1), and a unipolar or bipolar output select bit (D0) that are applied to any command (from DATA IN)

except for command 1111b. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to

the input data register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion result

from the output data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles

long depending on the data-length selection in the input data register. Sampling of the analog input begins on the

fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK

sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Analog MUX

The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer

according to the input addresses shown in Table 2. The input multiplexer is a break-before-make type to reduce

input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on the falling

edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the

falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then

sampled and converted in the same manner as the external analog inputs. The first conversion after the device

has returned from the power-down state may not read accurately due to internal device settling.

20

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