TLV2553

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SLAS354C – SEPTEMBER 2001 – REVISED SEPTEMBER 2015

8.4.12 Chip-Select Input (CS)

CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not

necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data

transfer of several devices sharing the same bus.

When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing its

output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK is

inhibited, thus preventing any further change in the internal state.

When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce

time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)

for a minimum time before a new I/O cycle can start.

CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough

before the end of the current conversion cycle, the previous conversion result is saved in the internal output

buffer and shifted out during the next I/O cycle.

When CS is held low continuously for multiple cycles, the first data bit of the newly completed conversion occurs

on DATA OUT on the rising edge of EOC.

NOTE

the first cycle in the series still requires a transition CS from high to low. When a new

conversion is started after the last falling edge of I/O CLOCK, EOC goes low and the

serial output is forced low until EOC goes high again.

When CS is toggled between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On

each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in

the serial conversion result until the required number of bits has been output.

8.4.13 Power-Down Features

When command (D7–D4) 1110b is clocked into the input data register during the first four I/O CLOCK cycles, the

software power-down mode is selected. Software power down is activated on the falling edge of the fourth I/O

CLOCK pulse.

During software power-down, all internal circuitry is put in a low-current standby mode. No conversions is

performed. The internal output buffer keeps the previous conversion cycle data results, provided that all digital

be completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle,

the converter normally begins in the power-down mode. The device remains in the software power-down mode

until a valid input address (other than command 1110b or 1111b) is clocked in. Upon completion of that I/O cycle,

a normal conversion is performed with the results being shifted out during the next I/O cycle.

The ADC also has an auto power-down mode. This is transparent to users. The ADC gets into auto power-down

within 1 I/O CLOCK cycle after the conversion is complete and resumes, with a small delay, after an active CS is

sent to the ADC. The resumption is fast enough to be used between cycles.

Copyright © 2001–2015, Texas Instruments Incorporated

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