TLV2553

SLAS354C – SEPTEMBER 2001 – REVISED SEPTEMBER 2015

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8.4.9 LSB Out First

D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion

result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first

always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to

another, the current I/O cycle is never disrupted.

8.4.10 Bipolar Output Format

D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared to

0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result of an

When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion

bit. The bipolar data format is related to the unipolar format in that the MSBs are always each other’s

complement.

Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output

during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the

current I/O cycle is not affected.

8.4.11 EOC Output

Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning

and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after

the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the

converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O

CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes

low, the analog input signal can be changed without affecting the conversion result.

The EOC signal goes high again after the conversion is completed and the conversion result is latched into the

output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.

On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When

CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the

falling edge of CS.

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