C1

0.1 F

Decoupling Cap

GND

Analog

Supply

Sample

~50 pF

CDAC

Convert

REF+

REF–

VCC

TLV2553

www.ti.com

SLAS354C – SEPTEMBER 2001 – REVISED SEPTEMBER 2015

Feature Description (continued)

8.3.2 Reference

An external reference can be used through two reference input pins, REF+ and REF–. The voltage levels applied

to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale

reading respectively. The values of REF+, REF–, and the analog input should not exceed the positive supply or

be lower than GND consistent with the specified absolute maximum ratings. The digital output is at full scale

when the input signal is equal to or higher than REF+ and at zero when the input signal is equal to or lower than

REF–.

Figure 39. Reference Block Diagram

8.4 Device Functional Modes

8.4.1 Converter Operation

The operation of the converter is organized as a succession of three distinct cycles: 1) the data I/O cycle, 2) the

sampling cycle and 3) the conversion cycle. The first two are partially overlapped.

8.4.2 Data I/O Cycle

The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods,

depending on the selected output data length. During the I/O cycle, the following two operations take place

simultaneously. An 8-bit data stream consisting of address/command and configuration information is provided to

DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. DATA INPUT

is ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length of 8, 12,

or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising

edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling edge of

CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding

bit is clocked out on the falling edge of each succeeding I/O CLOCK.

8.4.3 Sampling Cycle

During the sampling cycle, one of the analog inputs is internally connected to the capacitor array of the converter

to store the analog input signal. The converter starts sampling the selected input immediately after the four

address/command bits have been clocked into the input data register. Sampling starts on the fourth falling edge

of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge of

the I/O CLOCK depending on the data-length selection.

Copyright © 2001–2015, Texas Instruments Incorporated

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