TLV2553_15 datasheet(8/36 Pages) TI1

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TLV2553

SLAS354C – SEPTEMBER 2001 – REVISED SEPTEMBER 2015

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6.8 Timing Requirements: VREF+ = 5 V

over recommended operating free-air temperature range, I/O CLOCK frequency = 15 MHz, VCC = 5 V, load = 25 pF (unless

otherwise noted)

MIN

TYP

MAX

UNIT

tw1

Pulse duration I/O CLOCK high or low

26.7

100000

tsu1

Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 32)

th1

Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 32)

tsu2

Setup time CS low before first rising I/O CLOCK edge(1) (see Figure 33)

th2

Hold time CS pulse duration high time (see Figure 33)

100

th3

Hold time CS low after last I/O CLOCK falling edge (see Figure 33)

th4

Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 34)

th5

Hold time CS high after EOC rising edge when CS is toggled (see Figure 37)

Load = 25 pF

Delay time CS falling edge to DATA OUT valid

td1

(MSB or LSB) (see Figure 31)

Load = 10 pF

td2

Delay time CS rising edge to DATA OUT high impedance (see Figure 31)

td3

Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 34)

td4

Delay time Last I/O CLOCK falling edge to EOC falling edge

td5

Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion

1.5

µs

tt1

Transition time I/O CLOCK (1)(see Figure 34)

µs

tt2

Transition time DATA OUT (see Figure 34)

tt3

Transition time INT/EOC, CL at 7 pF (see Figure 36)

2.4

tt4

Transition time DATA IN, CS

µs

MAX(tconvert) +

tcycle

Total cycle time (sample, conversion and delays)(1)

I/O period

µs

(8/12/16 CLKs)

Source impedance = 25

600

Source impedance = 100

650

Channel acquisition time (sample), at 1 k

Ω,(1)

tsample

(See Figure 1 through Figure 6)

Source impedance = 500

700

Source impedance = 1 k

1000

(1)

I/O CLOCK period = 8X [1/(I/O CLOCK frequency)] or 12X [1/(I/O CLOCK frequency)] or 16X [1/(I/O CLOCK frequency)] depends on I/O

format selected.

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