1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

GND

EOC

I/O CLOCK

DATA IN

DATA OUT

CS

REF +

REF –

AIN10

AIN9

TLV2553

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SLAS354C – SEPTEMBER 2001 – REVISED SEPTEMBER 2015

5 Pin Configuration and Functions

DW or PW Package

20-Pin SOIC or TSSOP

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

AIN0 to AIN10

1 to 9, 11, 12

I

Analog input. These 11 analog-signal inputs are internally multiplexed.

Chip select. A high-to-low transition on CS resets the internal counters and controls and

CS

15

I

enables DATA OUT, DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and

I/O CLOCK within a setup time.

Serial data input. The 4-bit serial data can be used as address selects the desired analog input

channel or test voltage to be converted next, or a command to activate other features. The

DATA IN

17

I

input data is presented with the MSB (D7) first and is shifted in on the first four rising edges of

the I/O CLOCK. After the four address/command bits are read into the command register

CMR, I/O CLOCK clocks the remaining four bits of configuration in.

3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state

when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the

DATA OUT

16

O

high-impedance state and is driven to the logic level corresponding to the MSB/LSB value of

the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the

logic level corresponding to the next MSB/LSB, and the remaining bits are shifted out in order.

End-of-convertions status. Used to indicate the end of conversion (EOC) to the host processor.

EOC

19

O

EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and

remains low until the conversion is complete and the data is ready for transfer.

Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all

GND

10

—

voltage measurements are with respect to GND.

Input /output clock. I/O CLOCK receives the serial input and performs the following four

functions:

1.

It clocks the eight input data bits into the input data register on the first eight rising edges

of I/O CLOCK with the multiplexer address available after the fourth rising edge.

2.

On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected

I/O CLOCK

18

I

multiplexer input begins charging the capacitor array and continues to do so until the last

falling edge of I/O CLOCK.

3.

The remaining 11 bits of the previous conversion data are shifted out on DATA OUT.

Data changes on the falling edge of I/O CLOCK.

4.

Control of the conversion is transferred to the internal state controller on the falling edge

of the last I/O CLOCK.

REF+

14

I/O

REF+. The maximum analog input voltage range is determined by the difference between the

voltage applied to terminals REF+ and REF–.

Negative reference voltage. The lower reference voltage value (nominally ground) is applied to

REF–

13

I/O

REF–. This pin is connected to analog ground (GND of the ADC) when internal reference is

used.

20

—

Positive supply voltage

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