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STM32F479AI 数据表(PDF) 129 Page - STMicroelectronics |
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STM32F479AI 数据表(HTML) 129 Page - STMicroelectronics |
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129 / 208 page ![]() DocID028010 Rev 2 129/208 STM32F479xx Electrical characteristics 187 Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. 5.3.19 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of – 5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 57. Table 55. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C conforming to ANSI/ESDA/JEDEC JS-001 2 2000 V VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 °C conforming to ANSI/ESD S5.3.1, LQFP176, LQFP208, UFBGA169, UFBGA176, TFBGA216 and WLCSP148 packages C3 250 1. Guaranteed based on test during characterization. Table 56. Electrical sensitivities(1) Symbol Parameter Conditions Class LU Static latch-up class TA = +105 °C conforming to JESD78A II level A 1. MSV on PA4 and PA5 is 5 V, versus 5.4 V on all IOs. |
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