ISL8117

3

FN8666.3

June 4, 2015

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Pin Configurations

ISL8117

16 LD 4x4 QFN

TOP VIEW

ISL8117

16 LD HTSSOP

TOP VIEW

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(RoHS Compliant)

PKG.

DWG. #

ISL8117FRZ

81 17FRZ

-40 to +125

16 Ld 4x4 QFN

L16.4x4A

ISL8117FVEZ

8117 FVEZ

-40 to +125

16 Ld HTSSOP

M16.173A

ISL8117EVAL1Z

Evaluation Board for HTSSOP

ISL8117DEMO1Z

Demonstration Board for HTSSOP

ISL8117EVAL2Z

Evaluation Board for QFN

ISL8117DEMO2Z

Demonstration Board for QFN

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin

plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8117. For more information on MSL please see techbrief TB363.

1

3

4

15

CLKOUT

MOD/SYNC

PGOOD

RT

16

14

13

2

12

10

9

11

6

57

8

UGATE

PHASE

ISEN

VCC5V

SGND

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

EXTBIAS

EN

CLKOUT

MOD/SYNC

PGOOD

RT

FB

SS/TRK

VIN

UGATE

PHASE

ISEN

VCC5V

LGATE/OCS

PGND

BOOT

SGND

Pin Descriptions

PIN #

(HTSSOP)

PIN #

(QFN)

PIN

NAME

FUNCTION

3

1

CLKOUT

Clock signal output. The frequency of the clock signal is the switching frequency set by the resistor from RT

to ground.

4

2

MOD/SYNC Dual function pin. Connect this pin to VCC5V to select diode emulation mode with pulse skipping at light-load.

While connected to ground or floating, the controller operates in PWM mode at light-load.

Connect this pin to an external clock for synchronization. The controller operates in PWM Mode at light-load

when synchronized with an external clock.

5

3

PGOOD

Open-drain logic output used to indicate the status of output voltage. This pin is pulled down when the output

is not within ±11% of the nominal voltage or the EN pin is pulled LOW.