ISL8117

14

FN8666.3

June 4, 2015

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Functional Description

General Description

The ISL8117 integrates control circuits for a synchronous buck

converter. The driver and protection circuits are also integrated to

simplify the end design.

The part has an independent enable/disable control line EN,

which provides a flexible power-up sequencing and a simple VIN

UVP implementation. The soft-start time is programmable by

adjusting the soft-start capacitor connected from SS/TRK.

The valley current mode control scheme with input voltage

feed-forward ramp simplifies loop compensation and provides

excellent rejection to input voltage variation.

Input Voltage Range

The ISL8117 is designed to operate from input supplies ranging

from 4.5V to 60V.

The input voltage range can be effectively limited by the

available minimum PWM off-time as shown in Equation 2.

Where,

path, including the lower FET, inductor and PC board.

upper FET, inductor and PC board resistances.

The maximum input voltage and minimum output voltage is

Equation 3.

Internal 5V Linear Regulator (VCC5V) and

External VCC Bias Supply (EXTBIAS)

All the ISL8117 functions can be internally powered from an

on-chip, low dropout 5V regulator or an external 5V bias voltage

via the EXTBIAS pin. Bypass the linear regulator’s output (VCC5V)

with a 4.7µF capacitor to the power ground. The ISL8117 also

employs an undervoltage lockout circuit, which disables all

regulators when VCC5V falls below 3.5V.

The internal LDO can source over 75mA to supply the IC, power

the low-side gate driver and charge the boot capacitor. When

driving large FETs at high switching frequency, little or no

regulator current may be available for external loads.

For example, a single large FET with 15nC total gate charge

requires 15nC x 300kHz = 4.5mA (15nC x 600kHz = 9mA). Also,

at higher input voltages with larger FETs, the power dissipation

across the internal 5V will increase. Excessive dissipation across

this regulator must be avoided to prevent junction temperature

rise. Thermal protection may be triggered if die temperature

increases above +160°C due to excessive power dissipation.

When large MOSFETs are used, an external 5V bias voltage can

be applied to the EXTBIAS pin to alleviate excessive power

dissipation. Voltage at the EXTBIAS pin must always be lower

than the voltage at the VIN pin to prevent biasing of the power

stage through EXTBIAS and VCC5V. An external UVLO circuit

might be necessary to guarantee smooth soft-starting.

The internal LDO has an overcurrent limit of typically 120mA. For

better efficiency, connect VCC5V to VIN for 5V ±10% input

applications.

Enable and Soft-start Operation

Pulling the EN pin high or low can enable or disable the controller.

When the EN pin voltage is higher than 1.6V, the controller is

enabled to initialize its internal circuit. After the VCC5V pin reaches

the UVLO threshold, ISL8117 soft-start circuitry becomes active.

The internal 2µA charge current begins charging up the soft-start

capacitor connected from the SS/TRK pin to GND. The voltage

error amplifier reference voltage is clamped to the voltage on the

SS/TRK pin. The output voltage thus rises from 0V to regulation as

SS/TRK rises from 0V to 0.6V. Charging of the soft-start capacitor

continues until the voltage on the SS/TRK pin reaches 3V.

Typical applications for ISL8117 use programmable analog

soft-start or SS/TRK pin for tracking. The soft-start time can be

set by the value of the soft-start capacitor connected from the

SS/TRK to GND. Inrush current during start-up can be alleviated

by adjusting the soft-starting time.

The typical soft-start time is set according to Equation 4:

than 1.5ms, an internal soft-start circuit of 1.5ms takes over the

soft-start.

PGOOD will toggle to high when the corresponding output is up

and in regulation.

Pulling the EN low disables the PWM output and internal LDO to

achieve low standby current. The SS/TRK pin will also be

Output Voltage Programming

The ISL8117 provides a precision 0.6V internal reference voltage

to set the output voltage. Based on this internal reference, the

output voltage can thus be set from 0.6V up to a level

determined by the input voltage, the maximum duty cycle and

the conversion efficiency of the circuit.

A resistive divider from the output to ground sets the output

voltage. The center point of the divider shall be connected to the

FB pin. The output voltage value is determined by Equation 5.



+

1t



--------------------------------------------------------------------------







–

+



(EQ. 2)





--------------------------------------------------------------









(EQ. 3)

0.6V

2

A

-----------





=

(EQ. 4)

0.6V

+

---------------------







=

(EQ. 5)