ISL8117

18

FN8666.3

June 4, 2015

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converter. The Type 2 amplifier, in addition to the pole at origin,

has a zero-pole pair that causes a flat gain region at frequencies

between the zero and the pole.

High amplifier zero frequency gain and modulator gain are

chosen to satisfy most typical applications. The crossover

frequency will appear at the point where the modulator

attenuation equals the amplifier high frequency gain. The only

task that the system designer has to complete is to specify the

output filter capacitors to position the load main pole

somewhere within one decade lower than the amplifier zero

frequency. With this type of compensation, plenty of phase

margin is easily achieved due to zero-pole pair phase ‘boost’.

Conditional stability may occur only when the main load pole is

positioned extremely to the left side on the frequency axis due to

excessive output filter capacitance. In this case, the ESR zero

placed within the 1.2kHz to 30kHz range gives some additional

phase ‘boost’. Some phase boost can also be achieved by

the divider that sets the output voltage value. Please refer to

“Output Voltage Programming” on page 14.

Layout Guidelines

Careful attention to layout requirements is necessary for

successful implementation of an ISL8117 based DC/DC

converter. The ISL8117 switches at a very high frequency and

therefore the switching times are very short. At these switching

frequencies, even the shortest trace has significant impedance.

Also, the peak gate drive current rises significantly in an

extremely short time. Transition speed of the current from one

device to another causes voltage spikes across the

interconnecting impedances and parasitic circuit elements.

These voltage spikes can degrade efficiency, generate EMI, and

increase device overvoltage stress and ringing. Careful

component selection and proper PC board layout minimizes the

magnitude of these voltage spikes.

There are three sets of critical components in a DC/DC converter

using the ISL8117: The controller, the switching power

components and the small signal components. The switching

power components are the most critical from a layout point of

view because they switch a large amount of energy, which tends

to generate a large amount of noise. The critical small signal

components are those connected to sensitive nodes or those

supplying critical bias currents. A multilayer printed circuit board

is recommended.

Layout Considerations

1. The input capacitors, upper FET, lower FET, inductor and

output capacitor should be placed first. Isolate these power

components on dedicated areas of the board with their

ground terminals adjacent to one another. Place the input

high frequency decoupling ceramic capacitors very close to

the MOSFETs.

2. If signal components and the IC are placed in a separate area

to the power train, it is recommend to use full ground planes

in the internal layers with shared SGND and PGND to simplify

the layout design. Otherwise, use separate ground planes for

power ground and small signal ground. Connect the SGND

and PGND together close to the IC. DO NOT connect them

together anywhere else.

3. The loop formed by the input capacitor, the top FET and the

bottom FET must be kept as small as possible.

4. Ensure the current paths from the input capacitor to the

MOSFET, to the output inductor and the output capacitor are

as short as possible with maximum allowable trace widths.

5. Place the PWM controller IC close to the lower FET. The LGATE

connection should be short and wide. The IC can be best

placed over a quiet ground area. Avoid switching ground loop

currents in this area.

6. Place VCC5V bypass capacitor very close to the VCC5V pin of

the IC and connect its ground to the PGND plane.

7. Place the gate drive components - optional BOOT diode and

BOOT capacitors - together near the controller IC.

8. The output capacitors should be placed as close to the load as

possible. Use short wide copper regions to connect output

capacitors to load to avoid inductance and resistances.

9. Use copper filled polygons or wide short traces to connect the

junction of upper FET, lower FET and output inductor. Also

keep the PHASE node connection to the IC short. DO NOT

unnecessarily oversize the copper islands for the PHASE

node. Since the phase nodes are subjected to very high dv/dt

voltages, the stray capacitor formed between these islands

and the surrounding circuitry will tend to couple switching

noise.

10. Route all high speed switching nodes away from the control

circuitry.

11. Create a separate small analog ground plane near the IC.

Connect the SGND pin to this plane. All small signal grounding

FIGURE 32. FEEDBACK LOOP COMPENSATION

1

2

 R



-------------------------------

10kHz

==

(EQ. 10)

1

2

 R



-------------------------------

600kHz

==

(EQ. 11)

F

PO

F ZFP

MODULATOR

EA

CONVERTER

TYPE 2 EA

GEA= 18dB

GM = 23.5 dB