SWCS049B datasheet(54/119 Pages) TI1

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TPS659110, TPS659112, TPS659113

TPS659114, TPS659118, TPS6591133

SWCS049Q – JUNE 2010 – REVISED MARCH 2016

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Product Folder Links: TPS659110 TPS659112 TPS659113 TPS659114 TPS659118 TPS6591133

Detailed Description

6.4

PWM and LED Generators

The TPS65911x device has two LED ON/OFF signal generators, LED1 and LED2. LED1 and LED2 have

independently controllable periods from 125 ms to 8 s and ON time from 62.5 to 500 ms. Within the

period, one or two ON pulses can be generated (control bit LED1(2)_SEQ). The user must take care to

program period and ON time correctly, because no limitation on selected values is imposed. LED1 and

LED2 signals can be routed to GPIO1 and GPO3 open-drain outputs, respectively. These GPIOs have a

current sink capability of 10 mA.

The PWM generator frequency and duty cycle are set by the PWM_FREQ and PWM_DUTY_CYCLE bits,

respectively. The PWM generator signal can be connected to the GPIO3 or GPIO8 output. The PWM

generator uses the 3-MHz clock, which is not available in off mode. To enable the PWM in sleep mode,

the I2CHS_KEEPON bit must be set to 1.

6.5

Dynamic Voltage Frequency Scaling and Adaptive Voltage Scaling Operation

Dynamic voltage frequency scaling (DVFS) operation: A supply voltage value corresponding to a targeted

frequency of the digital core supplied is programmed in VDD1_OP_REG or VDD2_OP_REG registers.

The slew rate of the voltage supply reaching a new VDD1_OP_REG or VDD2_OP_REG programmed

value is limited to 12.5 mV/µs, fixed value.

Adaptative voltage scaling (AVS) operation: A supply voltage value corresponding to a supply voltage

adjustment is programmed in VDD1_SR_REG or VDD2_SR_REG registers. The supply voltage is then

intended to be tuned by the digital core supplied, based its performance self-evaluation. The slew rate of

VDD1 or VDD2 voltage supply reaching a new programmed value is programmable though the

VDD1_REG or VDD2_REG register, respectively.

A serial control interface (optional mode for EN1 and EN2 pins) can be dedicated to voltage scaling

applications, to give dedicated access to the VDD1_OP_REG, VDD1_SR_REG and VDD2_OP_REG,

VDD2_SR_REG registers.

A general-purpose serial control interface (CTL-I2C) also gives access to these registers, if the

SR_CTL_I2C_SEL control bit is set to 1 in the DEVCTRL_REG register (default inactive).

Both control interfaces are compliant with HS-I2C specification (100 Kbps, 400 Kbps, or 3.4 Mbps).

6.6

32-kHz RTC Clock

The TPS65911x device can provide a 32-kHz clock to the platform through the CLK32KOUT output, when

a crystal is connected.

Alternatively, the device can accept a square-wave 32-kHz clock signal applied to OSC32IN input

(OSC32KOUT kept floating) and gate the clock to CLK32OUT. This clock must be present for any state of

the EPC except the NO SUPPLY state. The TPS65911x device also has an internal 32-kHz RC oscillator

to reduce the BOM if an accurate clock is not needed by the system.

Default selection of a 32-kHz RC oscillator versus 32-kHz crystal oscillator or external square-wave

32-kHz clock depends on the boot configuration setting for the CK32K_CTRL bit.

Switching from the 32-kHz RC oscillator to the 32-kHz crystal oscillator or external square-wave 32-kHz

clock can also be programmed though the DEVCTRL_REG register.

SWCS049B 数据表(PDF) 54 Page - Texas Instruments

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