SWCS049B datasheet(90/119 Pages) TI1

90 / 119 page

TPS659110, TPS659112, TPS659113

TPS659114, TPS659118, TPS6591133

SWCS049Q – JUNE 2010 – REVISED MARCH 2016

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Detailed Description

Bits

Field Name

Description

Type

Reset

VDD2_EN1

When control bit = 1:

When SCLSR_EN1 is high the supply voltage is programmed though

VDD2_OP_REG register, and it can also be programmed off.

When SCLSR_EN1 is low the supply voltage is programmed though

VDD2_SR_REG register, and it can also be programmed off.

When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is

working in low-power mode, if not tuned off through VDD2_SR_REG

When control bit = 0 No effect: Supply state is driven though registers

programming and the device state

VDD1_EN1

When 1:

When SCLSR_EN1 is high the supply voltage is programmed though

VDD1_OP_REG register, and it can also be programmed off.

When SCLSR_EN1 is low the supply voltage is programmed though

VDD1_SR_REG register, and it can also be programmed off.

When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is

working in low-power mode, if not tuned off though VDD1_SR_REG

When control bit = 0 no effect: supply state is driven though registers

programming and the device state

VIO_EN1

When control bit = 1, supply state is driven by the SCLSR_EN1 control

signal and is also defined though SLEEP_KEEP_RES_ON register

setting:

When SCLSR_EN1 is high the supply is on,

When SCLSR_EN1 is low:

- the supply is off (default) or the SMPS is working in low-power mode if

its corresponding control bit = 1 in SLEEP_KEEP_RES_ON register

When control bit = 0 No effect: SMPS state is driven though registers

programming and the device state

Table 6-64. EN2_LDO_ASS_REG

Address Offset

0x47

Physical Address

Instance

(RESET DOMAIN: TURNOFF

RESET)

Description

Configuration Register setting the LDO regulators, driven by the multiplexed SDASR_EN2 signal.

When control bit = 1, LDO regulator state is driven by the SDASR_EN2 control signal and is also

defined though SLEEP_KEEP_LDO_ON register setting:

When SDASR_EN2 is high the regulator is on,

When SCLSR_EN2 is low:

- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register

- the regulator is working in low-power mode if its corresponding control bit = 1 in

SLEEP_KEEP_LDO_ON register

When control bit = 0 no effect: LDO regulator state is driven though registers programming and the

device state

Any control bit of this register set to 1 will disable the I2C SR Interface functionality

Type

LDO3_EN2

LDO4_EN2

LDO7_EN2

LDO8_EN2

LDO5_EN2

LDO2_EN2

LDO1_EN2

LDO6_EN2

Bits

Field Name

Description

Type

Reset

LDO3_EN2